Abstract
This study examines the influence of process variation on the drive current (ION), leakage current (IOFF), and the \(\left(\frac{{I}_{ON}}{{I}_{OFF}}\right)\) ratio in three distinct Field Effect Diode (FED) structures as documented in previous research. Through TCAD simulations, a comprehensive factorial design was established, encompassing geometrical, doping, and work function parameters, resulting in over 4000 data points. The simulation outcomes were segmented into training and testing datasets and analyzed using linear regression and random forest methodologies. The objective was to discern patterns within the ION, IOFF, and \(\left(\frac{{I}_{ON}}{{I}_{OFF}}\right)\) values and to develop a predictive model to classify the parameters. Notably, linear regression was deemed apt for interpreting ION and \(\left(\frac{{I}_{ON}}{{I}_{OFF}}\right)\) ratios, while the random forest approach was more fitting for IOFF. A pivotal finding was the significant role of Silicon epilayer thickness in impacting ION, IOFF, and the \(\left(\frac{{I}_{ON}}{{I}_{OFF}}\right)\) ratio. Additionally, it was determined that the work function of the source gate (WFGs) and the length of the drain gate (LGd) are the next two significant parameters.
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05 December 2023
A Correction to this paper has been published: https://doi.org/10.1007/s12633-023-02795-8
References
Gupta KA, Anvekar DK, Venkateswarlu V (2012) Device characterisation of short channel devices and its impact on CMOS circuit design. Int J VLSI Des Comm Syst (VLSICS) 3(5):163–173. https://doi.org/10.5121/vlsic.2012.3514
Gupta KA, Anvekar DK, Venkateswarlu V (2012) A comparative study and analysis of short channel effects for 180 nm and new 45 nm transistors. Springer Journal book series in Advances in Intelligent and SoftComputing, 178, 377–387. https://doi.org/10.37591/jovdtt.v7i3.1
Chaudhry A, Kumar JM (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for Improved Reliability: A Review. IEEE Trans Device Mat Reliabil, 4:99–109. https://doi.org/10.48550/arXiv.1008.2427
Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288. https://doi.org/10.1109/5.915374
Hisamoto D et al (2000) FinFET-A self-aligned double- gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47(12):2320–2325. https://doi.org/10.1109/16.887014
Virani HG, Gundapaneni S, Kottantharayil A (2011) Double dielectric spacer for the enhancement of silicon p-channel tunnel field effect transistor performance. Jpn J Appl Phys. https://doi.org/10.1143/JJAP.50.04DC04
Colinge JP (2008) FinFETs and other multi-gate transistors, Springer. ISBN: 978–0–387–71751–7
Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Nazalov N, Doria RT (2010) Reduced electric field in Junctionless transistors. Appl Phys Lett 96:7. https://doi.org/10.1007/s10825-013-0455-x
Anne Vandooren, Nadine Collaert 2016 Tunnel FETs for lowpower electronics, IEEE, 0–13. https://doi.org/10.1109/S3S.2016.7804386
Raissi F (1996)A brief analysis of the field effect diode and breakdown transistor, IEEE Trans Electron Devices, 43, 362–365. https://doi.org/10.1109/16.481742
Salman AA, Beebe SG, Emam M, Pelella MM, Ioannou DE (2006) Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies, IEEE 948–5721. https://doi.org/10.1109/IEDM.2006.346971
Hashem SA, Jit S (2020) Double-gate field-effect diode: A novel device for improving digital - and - analog performance. IEEE Trans Electron Dev 67(1):1931–2233. https://doi.org/10.1109/TED.2019.2955638
Sheikhian I, Raissi F (2003) High-speed digital family using field effect diode. Electr Lett 39:345–347. https://doi.org/10.1049/el:20030251
Ghafouri T, Manavizadeh N (2020) Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS. Alexandria Eng J 59(5):3715–3729. https://doi.org/10.1016/j.aej.2020.06.026
Sheikhian I, Sharafi F (2019) Improved nanoscale field effect diode, Article in IET Circuits, Devices and Systems, ISSN, 1751–858x. https://doi.org/10.1049/iet-cds.2018.5138
Taghibakhsh F (2003) “The field effect diode”, semiconductor device research symposium, pp 236 in abstract book
Salman AA, Inc TI, Beebe SG (2006) Field Effect Diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies, Electron Devices Meeting IEDM’06. International. https://doi.org/10.1109/IEDM.2006.346971
Ghafouri T, Manavizadeh N (2020) "Noise-Immune 6T SRAM Bit-Cells based on side-contacted FED. In: IEEE Trans Electr Dev, 67, (12):5511–5519. https://doi.org/10.1109/TED.2020.3028342
Sharafi F, Orouji AA, Soroosh M (2021) The novel structure to enhancement Ion/Ioff ratio based on field effect diode. IEEE Trans Device Mater Reliab 21(3):389–393. https://doi.org/10.1109/TDMR.2021.3102105
Ghoreishi SS, Vadizadeh M, Yousefi R, Afzalian A (2022) Low-power ultradeep-submicrometer junctionless carbon nanotube field-effect diode. IEEE Trans Electron Devices 69(1):400–405. https://doi.org/10.1109/TED.2021.3131110
Sheikhian I (2022) Bulk field effect diode. IEEE Trans Electron Devices 69(9):5055–5058. https://doi.org/10.1109/TED.2022.3188234
Synopsys sentaurus device user guideversion J-2014.09
SPSS Base 15.0 User’s Guide (2006)
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The authors are thankful to the work supported by DAE, BRNS, Government of India.
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This work is supported by DAE, BRNS, Government of India.
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Sasikala Panneerselvam: Conceptualization, Investigation, validation, writing, writing- original draft. All authors read and approved the final manuscript. Supervision: Dr. Srinivasan Raj.
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Panneerselvam, S., S, S., Bhattacharjee, T. et al. Impact of Process Variation on Leakage and Drive Currents of FED Structures Using Linear Regression and Random Forest Algorithms. Silicon 16, 955–964 (2024). https://doi.org/10.1007/s12633-023-02703-0
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DOI: https://doi.org/10.1007/s12633-023-02703-0