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Comparative Study on Random Interface Traps-Induced Reliability of NC-FinFETs and FinFETs

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Abstract

Fin-type field-effect transistors (FinFETs) are vulnerable to the random interface trap (RIT)-induced reliability issue caused by the bias temperature instability and hot carrier injection, which adversely affects the device performance. In this study, the electrical characteristic fluctuations induced by RITs are analyzed and a comparison is performed between the negative-capacitance FinFETs (NC-FinFETs) and their FinFET counterparts using technology computer-aided design (TCAD) simulation. The number and position of the trapped charges are randomly distributed at the silicon/silicon oxide (Si/SiO2) interface following the Poisson statistics recorded for the assembly of 200 fabricated transistors. The results demonstrate that the electrical characteristic dispersions of both the NC-FinFETs and FinFETs increase with the increase in the RIT concentration. However, the off-state currents demonstrate an opposite trend for the NC-FinFETs and FinFETs. Additionally, some NC-FinFETs with RITs exhibit steeper subthreshold swing (SS) characteristics than those without traps. Electrical parameter fluctuations are simultaneously produced by both the devices by the position uncertainty under the same RIT concentrations. This issue can be overcome by the partial suppression ability of the NC-FinFET which suppresses RIT-induced reliability due to the amplified electrostatic potential.

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All data generated during this study are included in this article.

References

  1. Liang Y, Li X, Gupta SK et al (2018) Analysis of DIBL effect and negative resistance performance for NCFET based on a compact SPICE model. IEEE Trans Electron Devices 65:5525–5529

    Article  CAS  Google Scholar 

  2. Saeidi A, Jazaeri F, Stolichnov I et al (2016) Double-gate negative-capacitance MOSFET with PZT gate-stack on ultra thin body SOI: An experimentally calibrated simulation study of device performance. IEEE Trans Electron Devices 63:4678–4684

    Article  Google Scholar 

  3. Appleby DJR, Ponon NK, Kwa KSK et al (2014) Experimental observation of negative capacitance in ferroelectrics at room temperature. Nano Lett 14:3864–3868

    Article  CAS  PubMed  Google Scholar 

  4. Lin CI, Khan AI, Salahuddin S et al (2016) Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE trans electron devices 63:2197–2199

    Article  Google Scholar 

  5. Jo J, Shin C (2016) Negative capacitance field effect transistor with hysteresis-free sub-60-mV/decade switching. IEEE Electron Device Lett 37:245–248

    Article  CAS  Google Scholar 

  6. Kao MY, Lin YK, Agarwal H et al (2019) Optimization of NCFET by matching dielectric and ferroelectric nonuniformly along the channel. IEEE Electron Device Lett 40:822–825

    Article  CAS  Google Scholar 

  7. Rollo T, Esseni D (2018) Influence of interface traps on ferroelectric NC-FETs. IEEE Electron Device Lett 39:1100–1103

    Article  CAS  Google Scholar 

  8. Pathak Y, Malhotra B D, Chaujar R (2021) TCAD analysis and simulation of double metal negative capacitance fet (DM NCFET). 2021 Devices for Integrated Circuit (DevIC) IEEE, pp 224–228

  9. Amrouch H, Salamin S, Pahwa G et al (2019) Unveiling the impact of IR-drop on performance gain in NCFET-based processors. IEEE Trans Electron Devices 66:3215–3223

    Article  CAS  Google Scholar 

  10. Prakash O, Gupta A, Pahwa G et al (2020) Impact of interface traps on negative capacitance transistor: Device and circuit reliability. IEEE Journal of the Electron Devices Society 8:1193–1201

    Article  CAS  Google Scholar 

  11. Chauhan V, Samajdar DP (2021) Recent advances in negative capacitance FinFETs for low power applications: a review. IEEE Trans Ultrason Ferroelectr Freq Control 68:3056–3068

    Article  PubMed  Google Scholar 

  12. Ganguli T, Chanda M, Sarkar A (2022) Impact of interface trap charges on the performances of junctionless MOSFET in sub-threshold regime. Comput Electr Eng 100:107914

    Article  Google Scholar 

  13. Makarov A, Kaczer B, Chasin A et al (2019) Bi-modal variability of nFinFET characteristics during hot-carrier stress: A modeling approach. IEEE Electron Device Lett 40:1579–1582

    Article  CAS  Google Scholar 

  14. Park J, Shin C (2017) Impact of interface traps and surface roughness on the device performance of stacked-nanowire FETs. IEEE Trans Electron Devices 64:4025–4030

    Article  CAS  Google Scholar 

  15. Mahapatra S, Saha D, Varghese D et al (2006) On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans Electron Devices 53:1583–1592

    Article  CAS  Google Scholar 

  16. Sriram SR, Bindu B (2019) A physics-based 3-D potential and threshold voltage model for undoped triple-gate FinFET with interface trapped charges. J Comput Electron 18:37–45

    Article  Google Scholar 

  17. Yu Z, Zhang Z, Sun Z et al (2020) On the trap locations in bulk FinFETs after hot carrier degradation (HCD). IEEE Trans Electron Devices 67:3005–3009

    Article  CAS  Google Scholar 

  18. Chung E A, Nam K J, Nakanishi T, et al (2017) Investigation of hot carrier degradation in bulk FinFET. 2017 IEEE International Reliability Physics Symposium (IRPS) IEEE, pp XT-6.1-XT-6.4

  19. Kumar A, Tripathi MM, Chaujar R (2018) Reliability issues of In2O5Sn gate electrode recessed channel MOSFET: Impact of interface trap charges and temperature. IEEE Trans Electron Devices 65:860–866

    Article  CAS  Google Scholar 

  20. Jo H, Choi S, Rhee S et al (2017) An analytical model for the threshold voltage of intrinsic channel MOSFET having bulk trap charges. IEEE Trans Electron Devices 64:2113–2120

    Article  CAS  Google Scholar 

  21. Lho YH, Kim KY (2005) Radiation effects on the power MOSFET for space applications. ETRI J 27:449–452

    Article  Google Scholar 

  22. Gupta A, Bajpai G, Singhal P, et al (2021) Traps based reliability barrier on performance and revealing early ageing in negative capacitance FET. 2021 IEEE International Reliability Physics Symposium (IRPS) IEEE, pp 1–6

  23. Garg C, Chauhan N, Sharma A et al (2021) Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET IEEE Trans. Electron Devices 68:5298–5304

    Article  CAS  Google Scholar 

  24. Kuzum D, Park JH, Krishnamohan T et al (2011) The effect of donor/acceptor nature of interface traps on Ge MOSFET characteristics. IEEE Trans electron devices 58:1015–1022

    Article  CAS  Google Scholar 

  25. Sudarsanan A, Nayak K (2021) Immunity to random fluctuations induced by interface trap variability in Si gate-all-around N-nanowire field-effect transistor devices. J Comput Electron 20:1169–1177

    Article  CAS  Google Scholar 

  26. Sachid AB, Chen MC, Hu C (2016) FinFET with High-k Spacers for Improved Drive Current. IEEE electron device lett 37:835–838

    Article  CAS  Google Scholar 

  27. Ku H, Shin C (2017) Transient response of negative capacitance in P (VDF 0.75-TrFE 0.25) organic ferroelectric capacitor. IEEE Journal of the Electron Devices Society 5:232–236

    Article  CAS  Google Scholar 

  28. Song TK, Kim JS, Kim MH et al (2003) Landau-Khalatnikov simulations for the effects of external stresses on the ferroelectric properties of Pb (Zr, Ti) O3 thin films. Thin Solid Films 424:84–87

    Article  CAS  Google Scholar 

  29. Ota H, Ikegami T, Fukuda K, et al (2018) Multidomain dynamics of ferroelectric polarization and its coherency-breaking in negative capacitance field-effect transistors. 2018 IEEE International Electron Devices Meeting (IEDM) IEEE, pp 9.1. 1–9.1. 4

  30. Wu S Y, Lin C Y, Chiang M C, et al (2016) A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027 um2 high density 6-T SRAM cell for mobile SoC applications. 2016 IEEE International Electron Devices Meeting (IEDM), pp 2.6.1–2.6.4

  31. Pahwa G, Agarwal A, Chauhan YS (2018) Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior. IEEE Trans Electron Devices 65:5130–5136

    Article  CAS  Google Scholar 

  32. Sun X, Zhang Y, Xiang J et al (2021) The Effect of Interface Traps at the Si/SiO2 Interface on the Transient Negative Capacitance of Ferroelectric FETs IEEE Trans. Electron Devices 68:4735–4740

    Article  CAS  Google Scholar 

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Acknowledgements

This work is supported by the National Natural Science Foundation of China (grant 62071160), and Zhejiang Provincial Natural Science Foundation of China (grant LY22F040001).

Funding

This work is supported by the National Natural Science Foundation of China (grant 62071160), and Zhejiang Provincial Natural Science Foundation of China (grant LY22F040001).

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Authors and Affiliations

  1. School of Microelectronics, Hangzhou Dianzi University, Hangzhou, China

    Weifeng Lü, Caiyun Zhang, Dengke Chen, Ying Han & Weijie Wei

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  1. Weifeng Lü
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  2. Caiyun Zhang
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  3. Dengke Chen
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  4. Ying Han
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  5. Weijie Wei
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Contributions

Weifeng Lü followed up the whole work process and revised the draft. Caiyun Zhang came up with the idea, carried out the device design and simulation and wrote the draft. Dengke Chen provided new drawing methods. Weijie Wei helped the simulation process. Ying Han reviewed the draft. All authors approved the final manuscript.

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Correspondence to Weifeng Lü.

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Lü, W., Zhang, C., Chen, D. et al. Comparative Study on Random Interface Traps-Induced Reliability of NC-FinFETs and FinFETs. Silicon 15, 4481–4488 (2023). https://doi.org/10.1007/s12633-023-02371-0

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  • DOI: https://doi.org/10.1007/s12633-023-02371-0

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