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Interface Trap Charges Analysis on DC and High Frequency Characteristics of UTBB-FDSOI FET

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Abstract

In this paper, we have studied effect of localised charges on performance of UTBB FDSOI FET. Purpose behind this work is to understand the performance of UTBB FDSOI FET under the influence of interface trap charges which are generated due to radiation or stress induced damage. These localised charges may affect operating point of transistor and affect the circuit reliability. Various figure of merits such as transconductance, second order transconductance, drain conductance and RF parameters like cut off frequency and gain bandwidth product have been studied in presence of localised charges. It is found that the interface trap affects the performance in subthreshold region more severely as compared to triode and saturation region. These charges always reside in interface between silicon and silicon di oxide, hence study of devices with these charges are essential in order to optimize the effect of these charges accordingly.

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Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

References

  1. Whitney J, Delforge P (2014) Data center efficiency assessment. Available online: http://www.nrdc.org/energy/files/data-center-efficiency-assessment-IP.pdf. National resource defense council, Aug 2014. Retrieved: 5 May, 2015

  2. Faynot O, Andrieu F, Weber O, Fenouillet-Béranger C, Perreau P, Mazurier J, Benoist T, Rozeau O, Poiroux T, Vinet M, Grenouillet L, Noel J-P, Posseme N, Barnola S, Martin F, Lapeyre C, Cassé M, Garros X, Jaud M-A et al (2010) Planar fully depleted SOI technology: A powerful architecture for the 20nm node and beyond. 2010 international electron devices meeting, San Francisco, CA, pp 3.2.1–3.2.4

    Google Scholar 

  3. Weber O, Andrieu F, Mazurier J, Cassé M, Garros X, Leroux C, Martin F, Perreau P, Fenouillet-Béranger C, Barnola S, Gassilloud R, Arvet C, Thomas O, Noel J-P, Rozeau O, Jaud M-A, Poiroux T, Lafond D, Toffoli A et al (2010) Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX. 2010 international electron devices meeting, San Francisco, CA, p 3.4.13.4.4

    Google Scholar 

  4. Liu Q, Vinet M, Gimbert J, Loubet N, Wacquez R, Grenouillet L, Le Tiec Y, Khakifirooz A, Nagumo T, Cheng K, Kothari H, Chanemougame D, Chafik F, Guillaumet S, Kuss J, Allibert F, Tsutsui G, Li J, Morin P et al (2013) High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond. 2013 IEEE international electron devices meeting, Washington, DC, pp 9.2.1–9.2.4

    Chapter  Google Scholar 

  5. Roy K, Mahmoodi H, Mukhopadhyay S, Ananthan H, Bansai A, Cakici T (2006) Double-gate SOI devices for low-power and high-performance applications. Proc. 19th Int. Conf. VLSI Design, pp 445–452

    Google Scholar 

  6. Cai J, Ren Z, Majumdar A, Ning TH, Yin H, Park D-G, Haensch WE (2008) Will SOI have a life for the low-power market? 2008 IEEE Int. SOI Conf. Proc., pp 15–16

    Chapter  Google Scholar 

  7. Simoen E, Claeys C (1995) The cryogenic operation of partially depeleted silicon-on-insulator inverters. IEEE Trans. Electron Devices 42:1100–1105

    Article  Google Scholar 

  8. Li Y, Niu G, Cressler JD, Patel J, Liu ST, Reed RA, Mojarradi MM, Blalock BJ (2003) The operation of 0.35 partially depleted SOI CMOS technology in extreme environments. Solid-State Electron 47:1111–1115

    Article  CAS  Google Scholar 

  9. Trabzon L, Awadelkarim O (1989) Damage to n-MOSFETs from electrical stress relationship to processing damage and impact on device reliability. Microelectron Reliab 38(4):651e657

    Google Scholar 

  10. Poindexter EH (1989) MOS interface states: overview and physicochemical perspective. Semicond Sci Technol 4(12):961e969

    Article  Google Scholar 

  11. Chiang T (2011) A compact model for threshold voltage of surrounding gate MOSFETs with localized interface trapped charges. IEEE Trans Electron Devices 58(2):567e57

    Article  Google Scholar 

  12. Awadhiya B, Pandey S, Nigam K, Kondekar P (2017) Effect of ITC’s on linearity and distortion performance of junctionless tunnel field effect transistor. Superlattice Microst 111:293–301

    Article  CAS  Google Scholar 

  13. Liu Y, Kijima S, Sugimata E, Masahara M, Endo K, Matsukawa T, Ishii K, Sakamoto K, Sekigawa T, Yamauchi H, Takanashi Y, Suzuki E (2006) Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication. IEEE Trans Nanotechnol 5:723–726

    Article  Google Scholar 

  14. Singanamalla R, Lisoni J, Ferain I, Richard O, Carbonell L, Schram T, Yu HY, Kubicek S, De Gendt S, Jurczak M, De Meyer K (2006) Electrical and material evaluation of the MOCVD TiN as metal gate electrode for advanced CMOS technology. Mater Res Soc Symp Proc 917:174–197

    Article  Google Scholar 

  15. Andrieu F, Dupre C, Rochette F, Faynot O, Tosti L, Buj C, Rouchouze E, Casse M, Ghyselen B, Cayrefoureq I, Brevard L, Allain F, Barbe JC, Cluzel J, Vandooren A, Denorme S, Ernst T, Fenouillet-Beranger C, Jahan C et al (2006) 25 nm short and narrow strained FDSOI with TiN/HfO2 gate stack. 2006 Symp. VLSI Technol. Dig. Tech. Papers, pp 134–135

    Chapter  Google Scholar 

  16. Shimada H, Hirano Y, Ushiki T, Ino K, Ohmi T (1997) Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications. IEEE Trans Electron Devices 44:1903–1907

    Article  CAS  Google Scholar 

  17. Shang H, White MH (2000) An ultra-thin midgap gate FDSOI MOSFET. Solid State Electron 44:1621–1625

    Article  CAS  Google Scholar 

  18. Chen J, Maiti B, Connelly D, Mendicino M, Huang F, Adetutu O, Yu Y, Weddington D, Wu W, Canelaria J, Dow D, Tobin P, Mogab J (1999) 0.18 m metal gate fully-depleted SOI MOSFETs for advanced CMOS application. 1999 Symp. VLSI Technol. Dig. Tech. Papers, pp 25–26

    Google Scholar 

  19. Van Dort MJ, Woerlee PH, Walker AJ (1994) A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions. Solid-State Elec 37(3):411–414

    Article  Google Scholar 

  20. Venkatesh P, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Impact of Interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric. IEEE Trans Device Mater Reliab 17(1):245–252

    Article  CAS  Google Scholar 

  21. Gupta S, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Effect of Interface trap charges on performance variation of heterogeneous gate dielectric Junctionless-TFET. IEEE Trans Electron Devices 64(11):4731–4737

    Article  CAS  Google Scholar 

  22. Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliab 16(2):227–234

    Article  CAS  Google Scholar 

  23. Gupta S, Sharma D, Soni D, Yadav S, Aslam M, Yadav DS, Nigam K, Sharma N (2018) Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability. Micro Nano Lett 13(8):1192–1196

    Article  CAS  Google Scholar 

  24. ATLAS (2015) Device simulation software. Silvaco Int, Santa Clara, CA, USA

    Google Scholar 

  25. Alam M (2013) ECE 695A Lecture 17: Subthreshold and Idlin Methods, https://nanohub.org/resources/16965

  26. Nigam K, Kondekar P, Sharma D (2016) DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor. Superlattice Microst 92:224–231

    Article  CAS  Google Scholar 

  27. Jaisawal RK, Rathore S, Kondekar PN, Yadav S, Awadhiya B, Upadhyay P, Bagga N (2022) Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques. Semicond Sci Technol 37(5):055010

    Article  Google Scholar 

  28. Yadav S, Awadhiya B, Mittal A (2022) Ohmic junction based tunnel FET for high frequency and low power applications. Silicon. https://doi.org/10.1007/s12633-022-01905-2

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All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by [Dr. Bhaskar Awadhiya], [Dr. Shivendra Yadav], and [Abhishek Acharya]. The first draft of the manuscript was written by [Dr. Bhaskar Awadhiya] and all authors commented, verified, checked and add on value to the previous versions of the manuscript by various means. All authors read and approved the final manuscript.

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Correspondence to Bhaskar Awadhiya.

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Awadhiya, B., Yadav, S. & Acharya, A. Interface Trap Charges Analysis on DC and High Frequency Characteristics of UTBB-FDSOI FET. Silicon 15, 937–942 (2023). https://doi.org/10.1007/s12633-022-02053-3

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