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Design and Comparative Analysis of Heterogeneous Gate Dielectric Nanosheet TFET with Temperature Variance

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Abstract

In this article, a Heterogeneous Gate-Dielectric Nanosheet Tunnel Field Effect Transistor (HD-NSH-TFET) with three channels is investigated using the 3-D Visual TCAD simulator. The HD layer of the proposed TFET consists of a high-k (HfO2) placed over the extended source and channel interface and a low-k (SiO2) at the extended drain and channel interface. An extensive comparison is outlined between the performance metrics of HD-NSH-TFET, conventional gate stack (GS)-NSH-TFET and negative capacitance nanosheet TFET(NC-NSH-TFET) configurations. The HD transistor exhibits an incredible leakage current of order 1e-18 A, while the gate stack demonstrates a leakage current of order 1e-16 A. The HD-NSH-TFET architecture ameliorates subthreshold swing (SS) and DIBL by 41.90 and 43.87 percent, respectively, over the GS structure. The HD-NSH-TFET device achieves a significant Ion/Ioff ratio (5.5e + 13), as well as an optimal subthreshold swing (13.88 mv/decade), while consuming minimal power and retaining excellent switching drivability. The effect of work function and oxide length on HD-NSH-TFET is investigated. The impact of temperature on DC and analogue parameters has been evaluated to ensure the device's reliability.

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Acknowledgements

We thank the Group, department of Electronics Technology, Guru Nanak Dev University, Amritsar for their interest in this work and useful comments to draft the final form of the paper. The support of CADRE Design Systems is gratefully acknowledged. We would like to thank Guru Nanak Dev University, Amritsar and Cadre Design Systems for lab facilities and research environment to carry out this work.

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Authors and Affiliations

  1. Department of Electronics Technology, Guru Nanak Dev University, Amritsar, Punjab, India

    Garima Jain, Ravinder Singh Sawhney & Ravinder Kumar

  2. Cadre Design Systems, Delhi, India

    Amit Saini

Authors
  1. Garima Jain
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  2. Ravinder Singh Sawhney
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  3. Ravinder Kumar
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  4. Amit Saini
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Contributions

All authors contributed to the design and simulation. Material preparation, data collection and analysis were performed by Garima Jain, Dr. Ravinder Singh Sawhney, Dr. Ravinder Kumar and Amit Saini. The first draft of the manuscript was written by Garima Jain and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Garima Jain.

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This study was approved by the university research ethics committee. All procedures per-formed in this study follow the ethical standards of the institutional and research committee.

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The authors have declared that no competing interests exist.

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Jain, G., Sawhney, R.S., Kumar, R. et al. Design and Comparative Analysis of Heterogeneous Gate Dielectric Nanosheet TFET with Temperature Variance. Silicon 15, 187–196 (2023). https://doi.org/10.1007/s12633-022-02013-x

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  • DOI: https://doi.org/10.1007/s12633-022-02013-x

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