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Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective

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Abstract

In this paper, for the first time, an optimized asymmetric U-shaped TFET, suitable for low power application, has been proposed after a hardcore performance analysis, considering the real-time adverse effect of gate/drain leakage phenomena known for deteriorating the subthreshold behaviour of a TFET. Two-level optimization – device-architecture level and gate-oxide level – remains the key factor of the work, ensuring its applicability even under extreme low power. For the proposed device with SiO2 as the material for asymmetric oxide arm, 7 nm turns out to be the optimized thickness, whereas it drops down to 5 nm and 4 nm, respectively, for Al2O3 and HfO2 arms. After a rigorous performance analysis, in terms of OFF-current, ON-current-OFF-current ratio, IDS-range for sub-60-mV/decade subthreshold swing, footprint, footprint-delay product, power-delay product, footprint-leakage-power density, the asymmetric TFET device with 5-nm asymmetric oxide arm of Al2O3 is found to be the most optimized device for the low power operation.

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Data Availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

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No funds, grants, or other support was received for conducting this study. The authors have no financial or proprietary interests in any material discussed in this article.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim Manipal University, East Sikkim, Sikkim, 737136, India

    Suman Das

  2. Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, West Bengal, 700009, India

    Suman Das, Avik Chattopadhyay & Suchismita Tewari

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  1. Suman Das
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  2. Avik Chattopadhyay
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Contributions

All the authors made substantial contribution to the conception and design of the work. Material preparation and data acquisition were performed by Suman Das; analysis or interpretation of data was done by Avik Chattopadhyay and Suchismita Tewari. The first draft of the manuscript was written by Suchismita Tewari and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Avik Chattopadhyay.

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Das, S., Chattopadhyay, A. & Tewari, S. Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective. Silicon 14, 10719–10727 (2022). https://doi.org/10.1007/s12633-022-01810-8

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