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Influence of structural and doping parameter variations on Si and \(\hbox {Si}_{1-x}\) \(\hbox {Ge}_{x}\) double gate tunnel FETs: An analysis for RF performance enhancement

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Abstract

This paper deals with the effect of structural and doping parameter variations on RF parameters for Si and \(\hbox {Si}_{1-x}\hbox {Ge}_{x}\)-based double gate (DG) tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. The DC parameter subthreshold swing (SS) and RF parameter metrics, unity gain cut-off frequency (\(f_{\mathrm{t}}\)) and maximum oscillation frequency (\(f_{\mathrm{max}}\)) are extracted by varying structural parameters, gate length (\(L_{\mathrm{g}}\)), gate oxide thickness (\(t_{\mathrm{ox}}\)), channel thickness (\(t_{\mathrm{ch}}\)), doping parameters, channel doping (\({{N}}_{\mathrm{ch}}\)), drain doping (\(N_{\mathrm{d}}\)) and source doping (\(N_{\mathrm{s}}\)) in and around their nominal value. For a channel thickness of 15 nm, a very less SS of 8 mV / dec is achieved in \(\hbox {Si}_{1-x}\hbox {Ge}_{x}\)-based DG TFETs with gate-drain overlap. Variations of gate oxide thickness offer better RF performance enhancement for Si-based asymmetric gate oxide devices. This could be achieved because of the higher tunnelling rate of electrons occurring at the source side of asymmetric gate oxide devices.

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References

  1. Y Khatami and K Banerjee, IEEE Trans. Electron Devices 56, 2752 (2009)

    Article  ADS  Google Scholar 

  2. P S Gupta, S Kanungo, H Rahaman, K Sinha and P S Dasgupta, Int. J. Appl. Phys. Math. 2, 240 (2012)

    Article  Google Scholar 

  3. A C Seabaugh and Q Zhang, Proc. IEEE 98, 2095 (2010)

    Article  Google Scholar 

  4. K Boucart and A M Ionescu, IEEE Trans. Electron Devices 54, 1725 (2007)

    Article  ADS  Google Scholar 

  5. K-F Lee et al, NSTI Nanotechnol. 2, 65 (2010)

    ADS  Google Scholar 

  6. L Zhang, M Chan and F He, IEEE International Conference on Electron Devices and Solid-State Circuits (Hong Kong, 2010) p. 1

  7. S M Razavi, S H Zahiri and S E Hosseini, Pramana – J. Phys. 88, 58 (2017)

    Article  ADS  Google Scholar 

  8. A Hraziia, C Andrei, A Vladimirescu, A Amara and C Anghel, Solid State Electron. 70, 67 (2012)

    Article  ADS  Google Scholar 

  9. E-H Toh, G H Wang, L Chan, D Sylvester, C-H Heng, G S Samudra and Y-C Leo, Jpn. J. Appl. Phys. 47, 2593 (2008)

    Article  ADS  Google Scholar 

  10. Q T Zhao, J M Hartmann and S Mantl, IEEE Electron. Device Lett. 32, 1480 (2011)

    Article  ADS  Google Scholar 

  11. H W Kim, J H Kim, S W Kim, M-C Sun, E Park and B-G Park, Jpn. J. Appl. Phys. 53, Article ID 06JE12-1 (2014)

  12. S Richter et al, Solid State Electron. 98, 75 (2014)

    Article  ADS  Google Scholar 

  13. D B Abdi and M J Kumar, J. Electron Device Soc. 2, 187 (2014)

    Article  Google Scholar 

  14. Synopsys Sentaurus Device User Guide version J-2014.09

  15. S Poorvasha and B Lakshmi, International Conference on VLSI Systems, Architectures, Technology and Applications (2016)

  16. Y Zhu and M K Hudait, Nanotechnol. Rev. 2, 637 (2013)

    Article  Google Scholar 

  17. P Chaturvedi and M J Kumar, Jpn. J. Appl. Phys. 53, Article No. 074201 (2014)

  18. G Rawat, S Kumar, E Goel, M Kumar1, S Dubey and S Jit, J. Semicond. 35, 084001-1 (2014)

  19. N B Balamurugan, K Sankaranarayanan, P Amutha and M F John, J. Semicond. Technol. Sci. 8, 221 (2008)

    Article  Google Scholar 

  20. S Cho, J S Lee, K R Kim, B-G Park, J S Harris and I M Kang, IEEE Trans. Electron Devices 58, 4164 (2011)

    Article  ADS  Google Scholar 

  21. V Vijayvargiya and S K Vishvakarma, IEEE Trans. Nanotechnol. 13, 974 (2014)

    Article  ADS  Google Scholar 

  22. J Mo, E Lind and L E Wernersson, IEEE Electron Device Lett. 35, 515 (2014)

    Article  ADS  Google Scholar 

  23. Sushant S Suryagandh, Mayank Garg, M Gupta, Jason C S Woo, International Conference on Solid-state and Integrated Circuits Technology, Vol. 1, p. 153 (2004).

  24. J Y Song, W Y Choi, J H Park, J D Lee and B-G Park, IEEE Trans. Nanotechnol. 5, 186 (2006)

    Google Scholar 

  25. T A Bhat, M Mustafa and M R Beigh, J. Nano Electron. Phys. 7, Article No. 03010-1 (2015)

  26. A Nandi, A K Saxena and S Dasgupta, IEEE Trans. Electron Devices 60, 1529 (2013)

    Article  ADS  Google Scholar 

  27. B Lakshmi and R Srinivasan, Int. J. VLSI Design Commun. Syst. 1, 36 (2010)

    Article  Google Scholar 

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Acknowledgements

This work is supported by the Department of Science and Technology, Government of India under SERB scheme Grant No. SERB / F / 2660.

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Poorvasha, S., Lakshmi, B. Influence of structural and doping parameter variations on Si and \(\hbox {Si}_{1-x}\) \(\hbox {Ge}_{x}\) double gate tunnel FETs: An analysis for RF performance enhancement. Pramana - J Phys 91, 2 (2018). https://doi.org/10.1007/s12043-018-1577-2

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  • DOI: https://doi.org/10.1007/s12043-018-1577-2

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