Skip to main content
SpringerLink
Log in

Performance Analysis of Germanium-Silicon Vertical Tunnel Field-Effect Transistors (Ge-Si-VTFETs) for Analog/RF Applications

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The performance analysis of Ge-Si-VTFETs for analog/RF applications has been studied in this article under various gate dielectric materials. In the proposed device, Ge/Si materials were chosen as source/drain material to improve the ON-state current (ION), Subthershold Swing (SS) and OFF-state current (IOFF) respectively. The aim of this work is to investigate the analog/RF device performance under different gate dielectric on the proposed VTFETs. Device simulation shows that hetero junction enhances the carrier tunneling at the source-channel junction (JSC) thereby increasing the ION = 5.55 × 10−5 A/μm, IOFF = 2.12 × 10−17 A/μm, ION/IOFF ratio of 1012, SS =12.76 mV/dec, cut-off frequency (fT) = 180 GHz, Gain Bandwidth Product (GBP) =32.2 GHz for high-κ dielectric (HfO2). In addition, the aforementioned parameters were studied considering the SiO2 and Al2O3 as gate dielectric. The result shows that proposed Ge-Si based VTFETs offers significant improvements in analog/RF parameters against conventional VTFETs and it can be better alternative for future low power gadgets.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

Not applicable.

References

  1. Dennard RH, Gaensslen FH, Yu HN, Rideout VL, Bassous E, LeBlanc AR (1974) Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J Solid State Circuits 9(5):256–268

    Article  Google Scholar 

  2. Rabaey TM, Chandrakasan A, Nikolic B (2003) Digital integrated circuits: a design perspective. Pearson Education, Upper Saddle River

    Google Scholar 

  3. Neaman DA (2012) Semiconductor physics and devices: basic principles. McGraw-Hill, New York

    Google Scholar 

  4. Sze SM, Ng KK (2006) Physics of semiconductor devices. Wiley, Hoboken

    Book  Google Scholar 

  5. Taur Y, Ning TH (2013) Fundamentals of modern VLSI devices. Cambridge University Press, Cambridge

    Google Scholar 

  6. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373):329–337

    Article  CAS  PubMed  Google Scholar 

  7. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745

    Article  CAS  Google Scholar 

  8. Mamidala JK, Vishnoi R, Pandey P (2016) Tunnel field-effect transistors (TFET): modelling and simulation. John Wiley & Sons, Hoboken

    Book  Google Scholar 

  9. Saurabh S, Kumar MJ (2016) Fundamentals of tunnel field-effect transistors. CRC Press, Boca Raton

    Book  Google Scholar 

  10. Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110

    Article  CAS  Google Scholar 

  11. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733

    Article  CAS  Google Scholar 

  12. Kumar N, Raman A (2020) Design and analog performance analysis of charge-plasma based cylindrical GAA silicon nanowire tunnel field effect transistor. Silicon 12(11):2627–2634

    Article  CAS  Google Scholar 

  13. Saurabh S, Kumar MJ (2011) Novel attributes of a nanoscale dual material gate tunnel field effect transistor. IEEE Trans Electron Devices 58:404–410

    Article  CAS  Google Scholar 

  14. Shirazi SG, Karimi GR, Mirzakuchaki S (2019) GAA CNT TFETs structural engineering: a higher on current, lower ambipolarity. IEEE Trans Electron Devices 66(6):2822–2830

    Article  CAS  Google Scholar 

  15. Zhao H, Chen Y, Wang Y, Zhou F, Xue F, Lee JJIT (2011) InGaAs tunneling field-effect-transistors with atomic-layer-deposited gate oxides. IEEE Trans Electron Devices 58(9):2990–2995

    Article  CAS  Google Scholar 

  16. Tomioka K, Fukui T (2011) Tunnel field-effect transistor using InAs nanowire/Si heterojunction. Appl Phys Lett 98(8):083114

    Article  Google Scholar 

  17. Cui N, Liang R, Xu J (2011) Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation. Appl Phys Lett 98(14):142105

    Article  Google Scholar 

  18. Kim G, Lee J, Kim JH, Kim S (2019) High on-current Ge-channel heterojunction tunnel field-effect transistor using direct band-to-band tunneling. Micromachines 10(2):77

    Article  PubMed Central  Google Scholar 

  19. Singh G, Amin SI, Anand S, Sarin RK (2016) Design of Si0. 5Ge0. 5 based tunnel field effect transistor and its performance evaluation. Superlattice Microst 92:143–156

    Article  CAS  Google Scholar 

  20. Hanna AN, Hussain MM (2015) Si/Ge hetero-structure nanotube tunnel field effect transistor. J Appl Phys 117(1):014310

    Article  Google Scholar 

  21. Cherik IC, Mohammadi S (2021) Enhanced on-state current and suppressed ambipolarity in germanium-source dual vertical-channel TFET. Semicond Sci Technol 36(4):045020

    Article  CAS  Google Scholar 

  22. Abdi DB, Kumar MJ (2015) PNPN tunnel FET with controllable drain side tunnel barrier width: proposal and analysis. Superlattice Microst 86:121–125

    Article  CAS  Google Scholar 

  23. Abdi DB, Kumar MJ (2014) In-built N+ pocket pnpn tunnel field-effect transistor. IEEE Electron Device Lett 35(12):1170–1172

    Article  CAS  Google Scholar 

  24. Ramkumar K, Ramakrishnan VN (2020) Investigation of hetero buried oxide and gate dielectric PNPN tunnel field effect transistors. Silicon 13:4101–4108

    Article  Google Scholar 

  25. Jhaveri R, Nagavarapu V, Woo JC (2010) Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans Electron Devices 58(1):80–86

    Article  Google Scholar 

  26. ATLAS Device Simulation Software (2015) Silvaco, Santa Clara, CA, USA

  27. Tripathy MR, Singh AK, Samad A, Chander S, Baral K, Singh PK, Jit S (2020) Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications. IEEE Trans Electron Devices 67(3):1285–1292

    Article  CAS  Google Scholar 

  28. Memisevic E, Svensson J, Lind E, Wernersson LE (2017) InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors. IEEE Trans Electron Devices 64(11):4746–4751

    Article  CAS  Google Scholar 

  29. Moselund KE, Schmid H, Bessire C, Bjork MT, Ghoneim H, Riel H (2012) InAs–Si nanowire heterojunction tunnel FETs. IEEE Electron Device Lett 33(10):1453–1455

    Article  CAS  Google Scholar 

  30. Bryllert T, Wernersson LE, Froberg LE, Samuelson L (2006) Vertical high-mobility wrap-gated InAs nanowire transistor. IEEE Electron Device Lett 27(5):323–325

    Article  CAS  Google Scholar 

  31. Boucart K, Ionescu AM (2008) A new definition of threshold voltage in tunnel FETs. Solid State Electron 52(9):1318–1323

    Article  CAS  Google Scholar 

  32. Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Reliab 16(2):227–234

    Article  CAS  Google Scholar 

  33. Gedam A, Acharya B, Mishra GP (2021) An analysis of interface trap charges to improve the reliability of a charge-plasma-based nanotube tunnel FET. J Comput Electron 20(3):1157–1168

    Article  CAS  Google Scholar 

  34. Shrivastava V, Kumar A, Sahu C, Singh J (2016) Temperature sensitivity analysis of dopingless charge-plasma transistor. Solid State Electron 117:94–99

    Article  CAS  Google Scholar 

  35. Guenifi N, Rahi SB, Ghodbane T (2018) Rigorous study of double gate tunneling field effect transistor structure based on silicon. Mater Focus 7(6):866–872

    Article  CAS  Google Scholar 

  36. Chauhan SS (2018) Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation. Superlattice Microst 117:1–8

    Article  Google Scholar 

  37. Wang Q, Wang S, Liu H, Li W, Chen S (2017) Analog/RF performance of L-and U-shaped channel tunneling field-effect transistors and their application as digital inverters. Jpn J Appl Phys 56(6):064102

    Article  Google Scholar 

Download references

Acknowledgements

We thank VIT University, Vellore for supporting this research work to carry out simulation using TCAD Simulator.

Funding

The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

Author information

Authors and Affiliations

  1. School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, India

    K. Ramkumar & V. N. Ramakrishnan

Authors
  1. K. Ramkumar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. V. N. Ramakrishnan
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors contributed to the study conception and design. Data collection, draft of the manuscript and analysis were performed by [Ramkumar K]. The validation of results and supervision [V.N. Ramakrishnan]. All authors read and approved the final manuscript.

Corresponding author

Correspondence to V. N. Ramakrishnan.

Ethics declarations

Ethics Approval

The authors confirm that this manuscript is original, has not been published elsewhere and is not under consideration by another journal.

Consent to Participate

All authors freely agreed and gave their consent to participate.

Consent for Publication

All authors freely agreed and gave their consent for the publication of this manuscript.

Competing Interests

The authors have no relevant financial or non-financial interests to disclose.

Research Involving Human Participants and/or Animals

Not applicable.

Informed Consent

Not applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ramkumar, K., Ramakrishnan, V.N. Performance Analysis of Germanium-Silicon Vertical Tunnel Field-Effect Transistors (Ge-Si-VTFETs) for Analog/RF Applications. Silicon 14, 10603–10612 (2022). https://doi.org/10.1007/s12633-022-01802-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-01802-8

Keywords

Search

Navigation