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All-Optical Parallel Programmable Logic Element Based on Binary Decision Diagram Mapping in Micro-Ring Resonators

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Abstract

An all-optical parallel programmable logic element (PPLE) has been proposed using three silicon micro-ring resonators (MRRs) in this paper. The circuit has three inputs and three outputs. Also three control inputs are used to change the output. Three outputs of the circuit exhibit one/two/three-variable binary logic functions. The device operates in μs range. Numerical simulation has been done to clarify the circuit performance. Extinction ratio and contrast ratio are found ~13 dB and 17 dB respectively. To find out the logical expressions at the output ports binary decision diagram (BDD) mapping is used. Comparisons with the existing MRR based logic circuits have also been done. The cascading mechanism is also shown to construct multivariable logical operations.

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  1. Mechanical Operation (Stage-II), Sagardighi Thermal Power Project, WBPDCL, Manigram, Murshidabad, West Bengal, 742237, India

    Tanay Chattopadhyay

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TC - Conceptualization, Methodology, implementation, simulation and writing original draft preparation.

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Chattopadhyay, T. All-Optical Parallel Programmable Logic Element Based on Binary Decision Diagram Mapping in Micro-Ring Resonators. Silicon 14, 10695–10718 (2022). https://doi.org/10.1007/s12633-022-01797-2

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