Skip to main content
Log in

A Novel Technique to Investigate the Impact of Temperature and Process Parameters on Electrostatic and Analog/RF Performance of Channel Modulated Junctionless Gate-all-around (CM-JL-GAA) MOSFET

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The channel modulated junctionless gate all around (CM-JL-GAA) MOSFET improves the SCE’s with high graded doping of the channel region. Temperature effects on electrostatic and analog/RF performance of channel modulated junctionless gate all around (CM-JL-GAA) MOSFETs have been explored in this work throughout a temperature range of 200 K to 500 K. The channel length, gate oxide thickness, and gate oxide material of CM-JL-GAA MOSFET has been varied to understand the impact of process parameters on device performance using Silvaco 3D device simulator. The electrostatic and analog/RF parameters have been figure out for the specified temperature range with process parameter variation. When the temperature of CM-JL-GAA MOSFETs is increased from 200 K to 500 K, the analog/RF performance is marginally affected. The intrinsic gain (AV) is negligibly affected (~3 dB) with raised in temperature. The adoption of a high-k gate dielectric improves electrostatic performance such as DIBL, SS and Ion/Ioff and marginal deterioration in the analog/RF performance of CM-JL-GAA MOSFETs, according to this study. With temperature changes, the high-k dielectric has a minor impact on the analog/RF performance of CM-JL-GAA MOSFETs. Hence, the CM-JL-GAA MOSFETs device have better analog/RF performance at higher temperature with high-frequency applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

Data Availability

The data and material are available within the manuscript.

References

  1. Kim JJ, Roy K (2014) Double gate-MOSFET subthreshold circuit for ultralow power applications. IEEE Trans Electron Devices 51:1468–1474

    Article  Google Scholar 

  2. Reddy G (2005) Venkateshwar, and M. J. Kumar, “a new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation”. IEEE Trans Nanotechnol 4:260–268

    Article  Google Scholar 

  3. Chiang TK (2013) A novel quasi-3-D threshold voltage model for fully depleted quadruple-gate (FDQG) MOSFETs: with equivalent number of gates (ENG) included. IEEE Trans Nanotechnol 12:1022–1025

    Article  CAS  Google Scholar 

  4. Jiménez D, Sáenz JJ, Iniguez B, Suñé J, Marsal LF, Pallares J (2004) Modeling of nanoscale gate-all-around MOSFETs. IEEE Electron Device Lett 25:314–316

    Article  Google Scholar 

  5. Tiwari PK, Dubey S, Singh K, Jit S (2012) Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs. Superlattice Microst 51(5):715–724

    Article  CAS  Google Scholar 

  6. Sreenivasulu VB, Narendar V (2021) Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length. Int J Electron Commun 137:153803

    Article  Google Scholar 

  7. Bousari NB, Anvarifard MK, Nasiri SH (2019) Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering. Int J Electron Commun 108:226–234

    Article  Google Scholar 

  8. Chang CY, Jhan YR, Wu JJ, Chen HB, Cheng YC, Wu YC (2013) Performance comparison between bulk and SOI junction less transistors. IEEE Electron Device Lett 34:169–171

    Article  Google Scholar 

  9. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, Neill BO, Blake A, White M, Kelleher A, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Technol 5:225–229

    CAS  Google Scholar 

  10. Sahay S, Kumar MJ (2019) Junction less field effect transistor: Design, Modeling, and Simulation. IEEE Press Series in Microelectronic system Wiley, pp. 1–496

  11. Park CH, Ko MD, Kim KH, Baek RH, Sohn CW, Baek CK, Park S, Deen MJ, Jeong YH, Lee JS (2012) Electrical characteristics of 20-nm junctionless Si nanowire transistors. Solid State Electron 73:7–10

    Article  CAS  Google Scholar 

  12. Colinge JP, Lee CW, Akhavan ND, Yan R, Ferain I, Razavi P, Kranti A, Yu R (2011) Junctionless transistors: physics and properties. Semiconductor-On-Insulator Materials for Nanoelectronics, pp. 187–200

  13. Rai MK, Gupta A, Rai S (2021) Comparative Analysis & Study of various leakage reduction techniques for Short Channel devices in Junctionless transistors: a review and perspective. Silicon. https://doi.org/10.1007/s12633-021-01181-6

  14. Kumar A, Gupta A, Rai S (2018) Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based Junctionless transistor. Int J Electron Commun 95:162–169

    Article  Google Scholar 

  15. Hu G, Xiang P, Ding Z, Liu R, Wang L, Tang TA (2014) Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding-gate transistors. IEEE Trans Electron Devices 61(3):688–695

    Article  Google Scholar 

  16. Purwar V, Gupta R, Kumar N, Awasthi H, Dixit VK, Singh K, Dubey S, Tiwari PK (2020) Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs. Appl Phys A Mater Sci Process 126:746

    Article  CAS  Google Scholar 

  17. Gnudi A, Reggiani S, Gnani E, Baccarani G (2013) Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Trans Electron Devices 60:1342–1348

    Article  Google Scholar 

  18. Chiang TK (2012) A quasi-two-dimensional threshold voltage model for Short-Channel Junctionless. IEEE Trans Electron Devices 59:2284–2289

    Article  Google Scholar 

  19. Gupta A, Rai S (2017) Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications. Microelectron J 64:60–68

    Article  Google Scholar 

  20. Agrawal AK, Koutilya PNVR, Kumar MJ (2015) A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor. J Comput Electron 14:686–693

    Article  CAS  Google Scholar 

  21. Kumari V, Modi N, Saxena M, Member S (2015) Theoretical investigation of dual material Junctionless double gate transistor for analog and digital performance. IEEE Trans Electron Devices 62:2098–2105

    Article  Google Scholar 

  22. Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S (2016) Analytical modeling of channel potential and threshold voltage of double-gate Junctionless FETs with a vertical Gaussian-like doping profile. IEEE Trans Electron Devices 63:2299–2305

    Article  CAS  Google Scholar 

  23. Kumari V, Kumar A, Saxena M, Member S (2018) Empirical model for nonuniformly doped symmetric double-gate Junctionless transistor. IEEE Trans Electron Devices 65:314–321

    Article  CAS  Google Scholar 

  24. Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D analytical modeling of threshold voltage for Graded-Channel dual material double-gate MOSFETs. IEEE Trans Electron Devices 63:966–973

    Article  CAS  Google Scholar 

  25. Chen Y, Mohamed M, Jo M, Ravaioli U, Xu R (2013) Junctionless MOSFETs with laterally graded-doping channel for analog / RF applications. J Comput Electron 12:757–764

    Article  CAS  Google Scholar 

  26. Duksh YS, Singh B, Gola D, Tiwari PK, Jit S (2020) Subthreshold modeling of graded channel double gate junctionless FETs. Silicon 13:1231–1238

    Article  Google Scholar 

  27. Gupta V, Awasthi H, Kumar N, Pandey AK, Gupta A (2021) A novel approach to model threshold voltage and subthreshold current of graded-doped junctionless-gate-all around (GD-JL-GAA) MOSFET. Silicon

  28. Gupta V, Kumar N, Awasthi H, Rai S, Pandey AK, Gupta A (2021) Temperature-dependent analytical modeling of graded-channel gate-all-around (GC-GAA) junctionless field-effect transistors (JLFETs). J Electron Mater

  29. D. Querlioz, J. S. Martin, K. Huet, A. Bournet, V. Aubry-Fortuna, C. Chassat, et al., “On the ability of the particle Monte Carlo technique quantum effects in nano-MOSFET simulation”, Trans Electron Devices, vo. 59, pp. 2232–2242, 2007

  30. Kumar N, Purwar V, Awasthi H, Gupta R, Singh K, Dubey S (2021) Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs. Microelectron J 113:105104

    Article  CAS  Google Scholar 

  31. Kumar N, Awasthi H, Purwar V, Gupta A, Dubey S (2021) Impact of temperature variation on analog, hot-carrier injection and linearity parameters of nanotube junctionless double-gate-all-around (NJL-DGAA) MOSFETs. Silicon

  32. Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP (2010) High-temperature performance of silicon junctionless MOSFETs. IEEE Trans Electron Devices 57(3):620–625

    Article  CAS  Google Scholar 

  33. Rassekh A, Jazaeri F, Fathipour M, Sallese JM (2019) Modeling interface charge traps in junctionless FETs, including temperature effects. IEEE Trans Electron Devices 66(11):4653–4659

    Article  CAS  Google Scholar 

  34. Pavanelloa MA, Cerdeirab A, Doriaa RT, Ribeiroa TA, Herrerab FÁ, Estrada M (2019) Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range. Solid State Electron 159:116–122

    Article  Google Scholar 

  35. Tayal S, Nandi A (2018) Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance. Cryogenics, Elsevier 92:71–75

    Article  CAS  Google Scholar 

Download references

Acknowledgements

Not Applicable.

Funding

This work did not receive financial support.

Author information

Authors and Affiliations

Authors

Contributions

All authors have made substantial contributions to the conception and design, or acquisition of data, or analysis and interpretation of data; have been involved in drafting the manuscript or revising it critically for important intellectual content, and have given final approval of the version to be published. Each author has participated sufficiently in work to take public responsibility for appropriate portions of the content. All authors read and approved the final manuscript.

Corresponding author

Correspondence to Amit Kumar Pandey.

Ethics declarations

The authors declare that all procedures followed were in accordance with the ethical standards.

Consent to Participate

All the authors declare their consent to participate in this research article.

Consent for Publication

All the authors declare their consent for publication of the article on acceptance.

Conflict of Interest

The authors declare that there is no conflict of interest regarding the publication of this paper.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gupta, A., Gupta, V., Pandey, A.K. et al. A Novel Technique to Investigate the Impact of Temperature and Process Parameters on Electrostatic and Analog/RF Performance of Channel Modulated Junctionless Gate-all-around (CM-JL-GAA) MOSFET. Silicon 14, 10613–10622 (2022). https://doi.org/10.1007/s12633-022-01794-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-01794-5

Keywords

Navigation