Abstract
In this paper, an analytical model has been developed for a single gate tunnel FET, introduced with a highly doped pocket in the vicinity of the source-channel junction and the bottom oxide layer being distributed between SiO2 and a high-k material such as HfO2. Introduction of the pocket region modifies the energy band diagram of the device thereby augmenting the electron tunneling from the source valence band to the channel conduction band in the band to band tunneling (BTBT) process of conduction. The proposed model results into an improvement in the surface potential, electric field profile and finally in the on state current Ion. Comparison of surface potential, electric fields for various Vgs has been made. Comparisons of the surface potential for various pocket widths, with and without the pocket & with & without the high-k dielectric material have also been made to show improvements in the proposed structure. Finally, drain current is computed and a comparison is made with & without the high-k dielectric material used in buried oxide.
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Vimala, P., ul Haque, M. & Usha, C. Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current. Silicon 14, 10383–10389 (2022). https://doi.org/10.1007/s12633-022-01778-5
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DOI: https://doi.org/10.1007/s12633-022-01778-5