Abstract
The leakage current is prime concern in the modern portable battery operated device. Therefore, various techniques using MOSFET and FinFET devices are presented and their performance is evaluated and compared. To further reduce the leakage current for improved battery backup in portable devices, new devices namely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. The subthreshold leakage power saving is observed in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25 °C) and high temperature (110 °C) with low and high input ranges. For high temperature & high input ranges, the simulation results show power saving from 89.65—97.86% and from 91.85—99.76% when compared with single chiral standard and LECTOR based domino circuits, respectively.
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References
Qin L (2007) Determination of the chiral indices (n, m) of carbon nanotubes by electron diffraction. Phys Chem Chem Phys 9:31–48. https://doi.org/10.1039/b614121h
Patel PK, Malik MM, Gupta TK (2018) Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region. J Comput Electron 17:774. https://doi.org/10.1007/s10825-017-1127-z
Ali. K, Chaudhary A R, Juanita, K. Roy, K. and De V. “Carbon Nanotube Field- Effect Transistors for High-Performance Digital Circuits-Transient Analysis, Parasitic, and Scalability” IEEE Transactions on Electron Devices 53(11)
Gupta TK, Khare K (2013) Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. J Circuits System and Signal Processing 32:2707–2722
Kao JT, Chandrakasan AP (2000) Dual-threshold voltage techniques for low-power digital circuits. IEEE J Solid-State Circuits 35(7):1009–1018. https://doi.org/10.1109/4.848210
Gupta TK, Pandey AK, Meena OP (2017) Analysis and design of lector-based dual-Vt domino logic with reduced leakage current. Circuit World 43(3):97–104. https://doi.org/10.1108/CW-03-2017-0013
Zhou Q, Zhao X, Cai Y, Hong X (2009) An MTCMOS technology for low-power physical design. Integration 42(3):340–345. https://doi.org/10.1016/j.vlsi.2008.09.004
Garg S, Gupta TK (2018) Low power domino logic circuits in deep-submicron technology using CMOS. Eng Sci Technol Int J 21(4):625–638. https://doi.org/10.1016/j.jestch.2018.06.013
Asyaei M (2015) A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron. Integr VLSI J 51:61–71
Nasserian M, Kafi-Kangi M, Maymandi-Nejad M, Moradi F (2016) A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates. Integr VLSI J 52:129–141
Moradi F, Cao TV, Vatajelu EI, Peiravi A, Mahmoodi H, Wisland DT (2013) Domino logic designs for high-performance and leakage-tolerant applications. Integration 46(3):247–254. https://doi.org/10.1016/j.vlsi.2012.04.005
Magraiya VK, Gupta TK (2019) ONOFIC pull-up approach in domino logic circuits using FinFET for subthreshold leakage reduction. Circuits Syst Signal Process 38:2564–2587. https://doi.org/10.1007/s00034-018-0980-8
Magraiya VK, Gupta TK (2019) ONOFIC-based leakage reduction technique for FinFET domino circuits. Int J Circ Theor Appl 47:217–237. https://doi.org/10.1002/cta.2583
Kumar A, Husain M, Khan A, Husain M (2014) Effect of parametric variation on the performance of single wall carbon nanotube based field effect transistor. Physica E 64:178–182
Tamersit K (2020) Sub-10 nm junctionless carbon nanotube field-effect transistors with improved performance. AEU-Int J Electron Commun 124:153354
Singh A, Khosla M, Raj B (2017) Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM. AEU-Int J Electron Commun 80:67–72
Shrivastava Y, Gupta TK (2020) Design of low power high speed CNFET 1 trit unbalanced ternary multiplier. Int J Numeric Model 33(1)
Shrivastava Y, Gupta TK (2021) Design of high-speed low variation static noise margin ternary S-RAM cells”. IEEE Trans Device Mater Reliab 21(1):102–110
Shrivastava Y, Gupta TK (2021) Design of compact reliable energy efficient read disturb free 17T CNFET Ternary S-RAM cell. IEEE Trans Device Mater Reliab 21(4):508–817
Stanford University CNTFET model website. Stanford, CA [Online] Available: Stanford University; 2008 https://nano.stanford.edu/model.php?id=23
Acknowledgements
I would like to express my deep and sincere gratitude to Head of Department Dr. Kavita Khare and Director MANIT Dr. N. S. Raghuvanshi, for their constant encouragement and valuable suggestions, which served as a source of inspiration for this work.
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Highlights
The major contributions of the paper are as follows:
1. A comprehensive analysis on the state-of-the-art leakage reduction techniques.
2. An analysis of the leakage reduction using CNTFET devices.
3. An improved leakage reduction technique using dual chiral CNTFET in standard footerless and LECTOR based domino circuits.
4. The simulation results show subthreshold leakage current reduction upto 97.3% at 25 °C and 99.76% at 110 °C.
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Magraiya, V.K., Gupta, T.K. & Garg, B. Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current. Silicon 14, 8695–8706 (2022). https://doi.org/10.1007/s12633-021-01623-1
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DOI: https://doi.org/10.1007/s12633-021-01623-1