Skip to main content
SpringerLink
Log in

Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

Recently, increasing power leakage has become a major concern especially in MOSFET based nanoscale devices due to poor gate control. To mitigate these problems, the devices with steep slope, low leakage and power consumption are required. In this context, this work introduced a novel concept of Negative Capacitance (NC) effect with Junctionless Multi Gate FET to investigate various device performance parameters for nanoscale dimensions. The baseline approach of combining LK-equation with Sentaurus TCAD tool, was used to design and optimize a 14nm n-type Negative Capacitance Junctionless FinFET (NC-JL FinFET) with doped HfO2 as gate ferroelectric material for low power applications. The impact of ferroelectric thickness, spacer and gate dielectric was analyzed using extensive device simulations. The results showed that the designed NC-JL FinFET exhibits enhanced performance with steep SS, Negative DIBL, lower leakage current and also higher drive current performance than JL FinFET. Further, the application of strain-engineering in NC-JL FinFET shows 12 % improvement in ION/IOFF as compared to unstrained NC-JL FinFET.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

Not Applicable.

Code Availability

Not Applicable.

References

  1. Gupta S, Steiner M, Aziz A, Narayanan V, Datta S, Gupta SK (2017) Device-circuit analysis of ferroelectric FETs for low-power logic. IEEE Trans Electron Devices 64:3092–3100. https://doi.org/10.1109/ted.2017.2717929

    Article  CAS  Google Scholar 

  2. Kobayashi M, Hiramoto T (2016) On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film. AIP Adv 6:025113. https://doi.org/10.1063/1.4942427

    Article  CAS  Google Scholar 

  3. Kobayashi M (2018) A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor. Appl Phys Express 11:110101. https://doi.org/10.7567/apex.11.110101

    Article  CAS  Google Scholar 

  4. Si M, Su C-J, Jiang C, Conrad NJ, Zhou H, Maize KD, Qiu G, Wu C-T, Shakouri A, Alam MA, Ye PD (2017) Steep-slope hysteresis-free negative capacitance MoS2 transistors. Nature Nanotech 13:24–28. https://doi.org/10.1038/s41565-017-0010-1

    Article  CAS  Google Scholar 

  5. Bal P, Akram MW, Mondal P, Ghosh B (2013) Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET). J Comput Electron 12:782–789. https://doi.org/10.1007/s10825-013-0483-6

    Article  Google Scholar 

  6. Solay LR, Singh S, Kumar N, Amin SI, Anand S (2020) Design of dual-gate P-type IMOS based industrial purpose pressure sensor. Silicon. https://doi.org/10.1007/s12633-020-00785-8

  7. Shukla N, Thathachary AV, Agrawal A, Paik H, Aziz A, Schlom DG, Gupta SK, Engel-Herbert R, Datta S (2015) A steep-slope transistor based on abrupt electronic phase transition. Nat Commun 6:7812. https://doi.org/10.1038/ncomms8812

    Article  CAS  PubMed  PubMed Central  Google Scholar 

  8. Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8:405–410. https://doi.org/10.1021/nl071804g

    Article  CAS  PubMed  Google Scholar 

  9. Khan AI, Chatterjee K, Wang B, Drapcho S, You L, Serrao C, Bakaul SR, Ramesh R, Salahuddin S (2014) Negative capacitance in a ferroelectric capacitor. Nature Mater 14:182–186. https://doi.org/10.1038/nmat4148

    Article  CAS  Google Scholar 

  10. Alam MA, Si M, Ye PD (2019) A critical review of recent progress on negative capacitance field-effect transistors. Appl Phys Lett 114:090401. https://doi.org/10.1063/1.5092684

    Article  CAS  Google Scholar 

  11. Peng Y, Liu Y, Han G, Zhang J, Hao Y (2019) Germanium negative capacitance field effect transistors: impacts of Zr composition in Hf1 – xZrxO2. Nanoscale Res Lett 14. https://doi.org/10.1186/s11671-019-2927-9

  12. Razavieh A, Zeitzoff P, Nowak EJ (2019) Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans Nanotechnol 18:999–1004. https://doi.org/10.1109/tnano.2019.2942456

    Article  CAS  Google Scholar 

  13. Colinge J-P, Lee C-W, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher A-M, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nature Nanotech 5:225–229. https://doi.org/10.1038/nnano.2010.15

    Article  CAS  Google Scholar 

  14. Rathore RS, Rana AK (2017) Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design. Superlattice Microst 110:68–81. https://doi.org/10.1016/j.spmi.2017.09.003

    Article  CAS  Google Scholar 

  15. Khan AI, Chatterjee K, Wang B, Drapcho S, You L, Serrao C, Bakaul SR, Ramesh R, Salahuddin S (2014) Negative capacitance in a ferroelectric capacitor. Nat Mater 14:182–186. https://doi.org/10.1038/nmat4148

    Article  CAS  PubMed  Google Scholar 

  16. Kaushal S, Rana AK, Sharma R (2021) Performance evaluation of negative capacitance junctionless FinFET under extreme length scaling. Silicon. https://doi.org/10.1007/s12633-020-00931-2

  17. Sentaurus TCAD, Synopsys (2017) https://www.synopsys.com

  18. Khan AI, Radhakrishna U, Salahuddin S, Antoniadis D (2017) Work function engineering for performance improvement in leaky negative capacitance FETs. IEEE Electron Device Lett 38:1335–1338. https://doi.org/10.1109/led.2017.2733382

    Article  CAS  Google Scholar 

  19. Pahwa G, Dutta T, Agarwal A, Chauhan YS (2018) Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures. IEEE Trans Electron Devices 65:867–873. https://doi.org/10.1109/ted.2018.2794499

    Article  CAS  Google Scholar 

  20. Li J, Liu Y, Han G, Zhou J, Hao Y (2019) Comparative study of negative capacitance field-effect transistors with different MOS capacitances. Nanoscale Res Lett 14:171. https://doi.org/10.1186/s11671-019-3013-z

    Article  CAS  PubMed  PubMed Central  Google Scholar 

  21. Lin C-I, Khan AI, Salahuddin S, Hu C (2016) Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans Electron Devices 63:2197–2199. https://doi.org/10.1109/ted.2016.2514783

    Article  Google Scholar 

  22. Agarwal H, Kushwaha P, Lin Y-K, Kao M-Y, Liao Y-H, Duarte J-P, Salahuddin S, Hu C (2018) NCFET design considering maximum interface electric field. IEEE Electron Device Lett 39:1254–1257. https://doi.org/10.1109/led.2018.2849508

    Article  CAS  Google Scholar 

  23. ITRS 2.0 International Technology Roadmap for Semiconductors (2013) http://www.itrs2.net. Accessed Jan 2021

  24. Kaundal S, Rana AK (2018) Design and structural optimization of junctionless FinFET with Gaussian-doped channel. J Comput Electron 17:637–645. https://doi.org/10.1007/s10825-018-1131-y

    Article  CAS  Google Scholar 

  25. Choi S-J, Moon D-I, Kim S, Duarte JP, Choi Y-K (2011) Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett 32:125–127. https://doi.org/10.1109/led.2010.2093506

    Article  CAS  Google Scholar 

  26. Seo J, Lee J, Shin M (2017) Analysis of drain-induced barrier rising in short-channel negative-capacitance FETs and its applications. IEEE Trans Electron Devices 64:1793–1798. https://doi.org/10.1109/ted.2017.2658673

    Article  Google Scholar 

  27. Liang Y, Li X, Gupta SK, Datta S, Narayanan V (2018) Analysis of DIBL effect and negative resistance performance for NCFET based on a compact SPICE model. IEEE Trans Electron Devices 65:5525–5529. https://doi.org/10.1109/ted.2018.2875661

    Article  CAS  Google Scholar 

  28. Kaushal S, Rana AK (2021) Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects. Superlattice Microst 155:106929. https://doi.org/10.1016/j.spmi.2021.106929

    Article  CAS  Google Scholar 

  29. Jiang C, Liang R, Wang J, Xu J (2016) Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric. Solid-State Electron 126:130–135. https://doi.org/10.1016/j.sse.2016.09.001

    Article  CAS  Google Scholar 

  30. Chen H-P, Lee VC, Ohoka A, Xiang J, Taur Y (2011) Modeling and design of ferroelectric MOSFETs. IEEE Trans Electron Devices 58:2401–2405. https://doi.org/10.1109/ted.2011.2155067

    Article  CAS  Google Scholar 

  31. Kaushal S, Kaundal S, Rana AK (2021) Impact of spacer configuration on negative capacitance multi gate junctionless FET. 2021 International Conference on Computer Communication and Informatics (ICCCI). https://doi.org/10.1109/iccci50826.2021.9402605

  32. McGuire FA, Lin Y-C, Price K, Rayner GB, Khandelwal S, Salahuddin S, Franklin AD (2017) Sustained sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors. Nano Lett 17:4801–4806. https://doi.org/10.1021/acs.nanolett.7b01584

    Article  CAS  PubMed  Google Scholar 

  33. Sharma R, Rathore RS, Rana AK (2017) Nanoscale static random-access-memory design using strained underlap ultra thin silicon on insulator MOSFET for improved performance. J Nanoelectron Optoelectron 12:359–364. https://doi.org/10.1166/jno.2017.2024a

    Article  CAS  Google Scholar 

  34. Sharma R, Rana AK, Kaushal S, King JB, Raman A (2021) Analysis of underlap strained silicon on insulator MOSFET for accurate and compact modeling. Silicon. https://doi.org/10.1007/s12633-021-01059-7

Download references

Acknowledgements

The authors would like to thank the Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur, Himachal Pradesh, India for providing valuable support to carry out this study in VLSI & Nano Laboratory.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT Hamirpur, Hamirpur, H.P., 177005, India

    Shelja Kaushal & Ashwani K. Rana

Authors
  1. Shelja Kaushal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ashwani K. Rana
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Design, Methodology, Formal analysis, and investigation, Validation, Writing - original draft preparation: [Shelja Kaushal]; Conceptualization, Resources, Supervision, Writing - review and editing: [Ashwani K. Rana]

Corresponding author

Correspondence to Shelja Kaushal.

Ethics declarations

Conflicts of Interest/Competing Interests

The authors have no relevant financial or non-financial interests to disclose.

Ethics Approval

Not Applicable.

Consent to Participate

Not Applicable.

Consent for Publication

Not Applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kaushal, S., Rana, A.K. Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach. Silicon 14, 6719–6728 (2022). https://doi.org/10.1007/s12633-021-01392-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-021-01392-x

Keywords

Search

Navigation