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Modeling and Simulation Based Investigation of Triple Material Surrounding Gate Tunnel FET for Low Power Application

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Abstract

A two-dimensional analytical model is proposed in this paper for surface potential and drain current on Triple Material Surrounding Gate Junctionless Tunnel Field Effect Transistor (TFET). The purpose of this theoretical analysis is to break down two 1D equations of the 2D Poisson Equations. In this model, Triple Material Gates are decomposed into three different individual gates with different work functions. The Finite Differentiation Method is being enforced for this reason. By applying sufficient boundary constraints, the decomposed individual 1D Poisson equations are combined. In essence, this decreases the difficulty of solving Poisson equations in 2D. The analytical model proposed makes expressions of surface potential and drain current simpler. The reduction in the subthreshold swing which makes the device useful for low power applications. Finally, the outcomes of the study are correlated with the TCAD simulation. The proposed model is therefore validated to explain the nature of the Triple Material Surrounding Gate Junctionless TFETs.

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Acknowledgments

The authors are grateful to the Management of “Thiagarajar college of Engineering”, Madurai for the support extended to carry out this research work.

Funding

We did not receive funding support from any organization for the submitted work and we certify that they have no affiliations with or involvement in any organization or entity with any financial interest or non-financial interest in the subject matter or materials discussed in this manuscript.

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Authors and Affiliations

  1. Department of CSE, Thiagarajar College of Engineering, Thiruparankundram, Tamil Nadu, 625015, India

    M. Suguna

  2. Department of ECE, Thiagarajar College of Engineering, Thiruparankundram, Tamil Nadu, 625015, India

    R. Kaveri, V. A. Nithya Sree, M. Hemalatha & N. B. Balamurugan

Authors
  1. M. Suguna
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  2. R. Kaveri
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  3. V. A. Nithya Sree
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  4. M. Hemalatha
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  5. N. B. Balamurugan
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Correspondence to M. Suguna.

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Suguna, M., Kaveri, R., Sree, V.A.N. et al. Modeling and Simulation Based Investigation of Triple Material Surrounding Gate Tunnel FET for Low Power Application. Silicon 14, 2363–2371 (2022). https://doi.org/10.1007/s12633-021-01368-x

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  • DOI: https://doi.org/10.1007/s12633-021-01368-x

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