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TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance

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Abstract

In this article, we investigated the impact of temperature variation on DC, analog, RF, and wireless performance of Gate Stack Gate All Around (GS-GAA) FinFET using SILVACO Atlas 3D simulator. The GAA structure introduction enhances the switching ratio (Ion/Ioff) by ∼152.37% and reduces the subthreshold swing (SS) by ∼6.5%. At gate voltage (Vgs) ∼ 0.725 V, the GS-GAA FinFET device exhibits the ZTC (Zero-Temperature-Coefficient) bias point, i.e., the effect of temperature on drain current gets nullified. DC parameters such as leakage current (Ioff), on current (Ion), SS, and threshold voltage (Vth) deteriorate with the rise in temperature. The enhancement in temperature degrades the RF and analog performance of the device by suppressing the parameters like transconductance (gm), device efficiency (TGF), cut-off frequency (fT), gain frequency product (GFP), gain-bandwidth product (GBP), etc. The device’s wireless performance is analyzed using linearity and harmonic distortion parameters such as gm3, gm2, 1-dB compression point, IIP3, VIP3, VIP2, IMD3, HD3, and HD2, and it shows significant improvement as the temperature increases from 300 K to 500 K.

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Acknowledgements

The authors acknowledge the Microelectronics Research Laboratory, Delhi Technological University, for assisting this research work.

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  1. Microelectronics Research Lab, Department of Applied Physics, Delhi Technological University, Delhi, India

    Bhavya Kumar & Rishu Chaujar

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Kumar, B., Chaujar, R. TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance. Silicon 13, 3741–3753 (2021). https://doi.org/10.1007/s12633-021-01040-4

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