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A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance

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Abstract

In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel field effect transistors (DL-DG-TFETs) with Si0.5Ge0.5 and Si as source material. The CP methodology resolves the issues of random doping fluctuation and doping activation. The analog and RF performance has been investigated for both the proposed devices i.e. Si0.5Ge0.5 source DL-DG-TFET and Si-source DL-DG-TFET in terms of drive current, transconductance, cut-off frequency. In addition, the linearity and distortion analysis has been carried out for both the proposed devices with respect to higher order transconductance (gm2 and gm3), VIP2, IMD3, and HD2. The Si0.5Ge0.5 source DL-DG-TFET has better performance characteristics and reliability in compare to Si-source DL-DG-TFET owing to low energy bandgap material and higher mobility. The switching ratio obtained for Si0.5Ge0.5 source DL-DG-TFET is order of 5 × 1014 that makes it a suitable contender for low power applications.

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Acknowledgments

Authors would like to thank Graphic Era (Deemed to be University) for their support and permission to communicate this research paper.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Graphic Era (Deemed to be University), Dehradun, 248002, India

    Varun Mishra & Vikas Rathi

  2. Department of Electronics and Communication Engineering, Lovely Professional University, Phagwara, India

    Yogesh Kumar Verma

  3. Department of Electronics and Communication Engineering, MNNIT Allahabad, Prayagraj, 211004, India

    Santosh Kumar Gupta

Authors
  1. Varun Mishra
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  2. Yogesh Kumar Verma
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  3. Santosh Kumar Gupta
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  4. Vikas Rathi
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All the authors have contributed in numerical calculation, framing, and writing the manuscript.

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Correspondence to Varun Mishra.

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Mishra, V., Verma, Y.K., Gupta, S.K. et al. A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance. Silicon 14, 2275–2282 (2022). https://doi.org/10.1007/s12633-021-01030-6

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