Abstract
Self-heating effects (SHE) in silicon-on-insulator (SOI) based tri-gate junctionless field effect transistor (TG-JLFET) due to low thermal conductivity of buried oxide (SiO2) is studied in this paper. Self-heating results in degradation of drain current due to reduced mobility and also negative differential conductance (NDC) is seen in saturation region. This paper shows that substrate bias voltage can dynamically reduce self-heating and NDC in TG-JLFETs. The analysis is carried out by three-dimensional TCAD simulation using Sentaurus device simulator.
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The authors declare that Deepti Gola has received research 179 support from Indian Institute of Technology Patna. Further, 180 authors have no other relevant funding or financial support 181 to disclose in relevance to the work shown in this paper.
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All authors contributed to the study conception and conceptualization. Material preparation, TCAD simulation and analysis were performed by Deepti Gola. Formal analysis and investigation of the simulated results were done by Yograj Singh Duksh and Pramod Kumar Tiwari. The first draft of the manuscript was written by Deepti Gola and edited by Balraj Singh and Pramod Kumar Tiwari. Moreover, all the authors commented on previous versions of the manuscript and the final manuscript was read and approved by all the authors. Finally, the complete work was carried under the supervision of Pramod Kumar Tiwari.
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The authors declare that Deepti Gola has received research support from Indian Institute of Technology Patna. Moreover, Pramod Kumar Tiwari is affiliated to Indian Institute of Technology Patna. Further, Yograj Singh Duksh and Balraj Singh are affiliated to M.J.P. Rohilkhand University Bareilly and G.B.Pant Institute of Engineering and Technology Pauri respectively. Further, authors have no other relevant financial/non-financial interests or personal relationships that could have appeared to influence the work reported in this paper to disclose.
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The authors declare that Deepti Gola has received research support from Indian Institute of Technology Patna. Moreover, Pramod Kumar Tiwari is affiliated to Indian Institute of Technology Patna. Further, Yograj Singh Duksh and Balraj Singh are affiliated to M.J.P. Rohilkhand University Bareilly and G.B.Pant Institute of Engineering and Technology Pauri respectively. Further, authors have no other relevant financial/non-financial interests or personal relationships that could have appeared to influence the work reported in this paper to disclose
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Gola, D., Duksh, Y.S., Singh, B. et al. Self-heating and Negative Differential Conductance Improvement by Substrate Bias Voltage in Tri-gate Junctionless Transistor. Silicon 14, 2219–2224 (2022). https://doi.org/10.1007/s12633-021-01019-1
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DOI: https://doi.org/10.1007/s12633-021-01019-1