Skip to main content
SpringerLink
Log in

Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

In this paper, to solve the problem of higher ambipolar leakage current (Iambipolar) of Dielectric Engineered (DE) Dopant Segregated (DG) Schottky Barrier (SB) MOSFET (DE DS SBMOS), we have incorporated dual metal gate (DMG) in place of single metal gate for the DE DS SBMOS. The proposed device is named as DMG DE DS SBMOS. In a proposed device, the gate is consisting of dual metal having different work functions. Therefore, the gate is divided in two parts named as auxiliary gate (AG) and tunneling gate (TG). AG and TG employed near the source and drain (S/D) ends, respectively. AG is mainly used to control the on-state performance and TG for the off-state performance by modulating the SB height and width at S/D end, respectively. Simulation results show that Iambipolar of the device has been successfully suppressed by choosing appropriate work functions for AG and TG without affecting the on-state current (Ion) of the device. The proposed device combines the advantage of dual metal gate and dielectric engineering to achieve improvement in the overall performance of the device. The proposed device exhibits high Ion, low Iambipolar and low subthreshold swing (SS). The simulations study verifies the use of the proposed device for low power applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Jhaveri R, Nagavarapu V, Woo JCS (2009) Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications. IEEE Trans Electron Devices 56(1):93–99. https://doi.org/10.1109/TED.2008.2008161

    Article  CAS  Google Scholar 

  2. Schwarz M, Calvet LE, Snyder JP, Krauss T, Schwalke U, Kloes A (2017) On the physical behavior of cryogenic IV and IIIV Schottky Barrier MOSFET devices. IEEE Trans Electron Devices 64(09):3808–3815

    Article  CAS  Google Scholar 

  3. Martín-Martínez MJ, Couso C, Pascual E, Rengel R (2014) Monte Carlo study of dopant-segregated Schottky barrier SoI MOSFETs: Enhancement of the RF performance. IEEE Trans Electron Devices 61(12):3955–3961. https://doi.org/10.1109/TED.2014.2360468

    Article  CAS  Google Scholar 

  4. Kale S (2020) Performance improvement and analysis of PtSi Schottky barrier p-MOSFET based on charge plasma concept for low power applications. Silicon 12:479–485

    Article  CAS  Google Scholar 

  5. Hema Latha NK, Kale S (2020) Dielectric modulated Schottky barrier TFET for the application as label-free biosensor. Silicon 12:2673–2679. https://doi.org/10.1007/s12633-019-00363-7

    Article  CAS  Google Scholar 

  6. Kale S, Kondekar PN (2015) Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering. Electron Lett 51(19):1536–1538. https://doi.org/10.1049/el.2015.0283

  7. Kale S, Kondekar PN (2015) Ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFET. IETE J Res 61(4):323–328. https://doi.org/10.1080/03772063.2015.1021387

    Article  Google Scholar 

  8. Valentin R, Dubois E, Larrieu G, Member J-P, Raskin G, Dambrine N, Breil F, Danneville (2009) Optimization of RF performance of metallic source/drain SOI MOSFETs using dopant segregation at the Schottky interface. IEEE Electron Device Lett 30(11):1197–1199

    Article  CAS  Google Scholar 

  9. Kumar P, Bhowmick B (2017) 2-D analytical modelling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET. J Comput Electron 16(3):658–665

    Article  Google Scholar 

  10. Kumar P, Bhowmick B (2018) Scaling of dopant segregation Schottky barrier using metal strip buried oxide MOSFET and its comparison with conventional device. Silicon 10(3):811–820

    Article  CAS  Google Scholar 

  11. Guin S, Chattopadhyay A, Karmakar A, Mallik A (2014) Impact of a pocket doping on the device performance of a Schottky tunneling field effect transistor. IEEE Trans Electron Dev 61(7):2515–2522. https://doi.org/10.1109/TED.2014.2325068

    Article  CAS  Google Scholar 

  12. Bashir F, Loan SA, Rafat M, Abdul Rahman M, Alamoud SA, Abbasi (2015) A high-performance source engineered charge plasma-based Schottky MOSFET on SOI. IEEE Trans Electron Devices 62(10):3357–3364

    Article  CAS  Google Scholar 

  13. Larson JM, Snyder JP (2006) Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans Electron Devices 53(5):1048–1058. https://doi.org/10.1109/TED.2006.871842

    Article  CAS  Google Scholar 

  14. Kale S, Kondekar PN (2015) Design and investigation of double gate Schottky barrier MOSFET using gate engineering. IET Micro Nano Lett 10(12):707–711. https://doi.org/10.1049/mnl.2015.0046

    Article  CAS  Google Scholar 

  15. Kale S, Kondekar PN (2016) Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation. Superlattice Microst 89:225–230. https://doi.org/10.1016/j.spmi.2015.11.019

    Article  CAS  Google Scholar 

  16. Kale S, Kondekar PN (2018) Charge plasma-based source/drain engineered Schottky Barrier MOSFET: Ambipolar suppression and improvement of the RF performance. Superlattice Microstruct 113:799–809

    Article  CAS  Google Scholar 

  17. Kale S, Banchhor S, Kondekar PN (2015) Performance study of high-k gate & spacer dielectric Dopant Segregated Schottky Barrier SOI MOSFET. 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, pp 1142–1145. https://doi.org/10.1109/ECS.2015.7124762

  18. Kale S. Investigation of dual metal gate Schottky barrier MOSFET for suppression of ambipolar current. IETE J Res. https://doi.org/10.1080/03772063.2020.1823250

  19. Kale S, Kondekar PN (2017) Design and investigation of dielectric engineered dopant segregated Schottky barrier MOSFET with NiSi source/drain. IEEE Trans Electron Devices 64(11):4400–4407

    Article  CAS  Google Scholar 

  20. Zhao QT, Rije E, Bruer U, Lenk S, and S. Mantl (2004) Tuning of silicide Schottky barrier heights by segregation of sulfur atoms. In: Proc. 7th Int. Conf. Solid-State Integr. Circuits Technol, pp 456–459

  21. (2014) ATLAS Device Simulation Software. Silvaco, Santa Clara

  22. Ieong M, Solomon PM, Laux SE, Wong H-SP, Chidambarrao D (1998) Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model. In: IEDM Tech. Dig., pp 733–736. https://doi.org/10.1109/IEDM.1998.746461.

  23. Matsuzawa K, Uchida K, Nishiyama A (2000) A unified simulation of Schottky and ohmic contacts. IEEE Trans Electron Devices 47(1):103–108. https://doi.org/10.1109/16.817574.

  24. Vega RA (2006) Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering. IEEE Trans Electron Devices 53(7):1593–1600. https://doi.org/10.1109/TED.2006.876261.

  25. Neamen DA (2003) Semiconductor physics and devices, 3rd ed. McGraw-Hill, New York

  26. Sze SM, Ng KK (2007) Physics of semiconductor devices. Wiley, Hoboken

  27. Banchhor S, Kale S, Kondekar PN (2015) Influence of underlap gate length on analog/RF performance of pocket doped Schottky Barrier MOSFET. 2015 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, pp 1152–1155. https://doi.org/10.1109/ECS.2015.7124764.

  28. Kale S, Banchhor S, Kondekar PN (2016) Impact of underlap channel on analog/RF performance of dopant segregated schottky barrier MOSFET on ultra-thin body SOI. 2016 International Conference on Emerging Trends in Engineering, Technology and Science(ICETETS), Pudukkottai, pp 1–6. https://doi.org/10.1109/ICETETS.2016.7603033.

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, 110042, India

    Sumit Kale

  2. Department of Electronics and Communication Engineering, Madanapalle Institute of Technology & Science, Madanapalle, AP, 517325, India

    Madduri Sai Chandu

Authors
  1. Sumit Kale
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Madduri Sai Chandu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sumit Kale.

Additional information

Publisher’s note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kale, S., Chandu, M.S. Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current. Silicon 14, 935–941 (2022). https://doi.org/10.1007/s12633-020-00921-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00921-4

Keywords

Search

Navigation