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Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization

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Abstract

A dopingless vertical Nanowire (NW) Tunnel Field Effect Transistor TFET structure has been designed using techniques such as Dual-Metal Gate (DMG), Heteromaterial Channel (HmC) and Heterodielectric Oxide (HdO) to enhance the device performance. The proposed device is investigated to acknowledge the device behavior for RF/Low-Noise applications. The essence of the reported work is to capture the effect of work function variation of DMG on device characteristics for noise enhancement/degradation. The vertical structure simplifies the implementation of charge-plasma technique for induced doping within the source/drain region enveloped by Gate-All-Around (GAA) architecture. Different work function combinations of gate metal1 (GM1) and gate metal2 (GM2) are used for calculations and compared to acquire optimized results. Other than Silicon, Silicon-Germanium compound (SixGe1-x) with composition factor (x) equals to 0.55 is used for HmC, whereas Zirconium Silicate is preferred for HdO. The characteristics analysis includes the negative drain bias variation that captures an interesting tunnel diode characteristics with peak current to valley current ratio of approx. 108. The proposed structure is modified to reduce the Gate-to-Source capacitive coupling and drain current enhancement. The proposed device is analyzed for Ambipolar-state, OFF-state and ON-state, which is required to understand the proper working of TFET devices.

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Authors and Affiliations

  1. VLSI Lab, Department of Electronics and Communications, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, 144011, India

    Naveen Kumar & Ashish Raman

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  1. Naveen Kumar
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  2. Ashish Raman
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Correspondence to Naveen Kumar.

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Kumar, N., Raman, A. Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization. Silicon 13, 3141–3151 (2021). https://doi.org/10.1007/s12633-020-00659-z

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  • DOI: https://doi.org/10.1007/s12633-020-00659-z

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