Abstract
The tunnel field-effect transistor (TFET) is considered a promising next-generation transistor due to its potentially limit-breaking low subthreshold swing and better immunity against short-channel effects. However, the low ON-state current (ION) of TFETs has been a critical problem. In this work, we investigated the effects of the source doping concentration and the source doping gradient (SDG) on the ION of n-type Si gate-all-around (GAA) nanowire (NW) TFETs using an ATLAS device simulator. Unexpectedly, we found that increasing the source doping concentration does not necessarily improve ION, especially for TFETs with a large SDG. Moreover, although reducing the SDG indeed increases ION, for TFETs with low source doping concentration (e.g., 1 × 1019 cm−3), the improvement in ION by reducing the SDG becomes insignificant.
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The datasets generated during and/or analyzed during the current study are available from the corresponding author on request.
References
Khatami, Y., Banerjee, K.: Steep subthreshold slope n- and p-Type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans. Electron Devices 56(11), 2752–2761 (2009). https://doi.org/10.1109/TED.2009.2030831
Seabaugh, A., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE. 98(12), 2095–2110 (2010). https://doi.org/10.1109/JPROC.2010.2070470
Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373), 329–337 (2011). https://doi.org/10.1038/nature10679
Lu, H., Seabaugh, A.: Tunnel field-effect transistors: state-of-the-art. J. Electron Devices Soc. 2(4), 44–49 (2014). https://doi.org/10.1109/JEDS.2014.2326622
Avci, U.E., Morris, D.H., Young, I.A.: Tunnel field-effect transistors: prospects and challenges. J. Electron Devices Soc. 3(3), 88–95 (2015). https://doi.org/10.1109/JEDS.2015.2390591
Verhulst, A.S., Vandenberghe, W.G., Maex, K., Groeseneken, G.: Tunnel field-effect transistor without gate-drain overlap. Applied Physics Letters. 91, 053102 (2007). https://doi.org/10.1063/1.2757593
Sandow, C., Knoch, J., Urban, C., Zhao, Q.-T., Mantl, S.: Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors. Solid-State Electron. 53, 1126–1129 (2009). https://doi.org/10.1016/j.sse.2009.05.009
Huang, R., Huang, Q., Chen, S., Wu, C., Wang, J., An, X., Wang, Y.: High performance tunnel field-effect transistor by gate and source engineering. Nanotechnology 25, 505201 (2014). https://doi.org/10.1088/0957-4484/25/50/505201
Yang, Z.: Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett. 37(7), 839–842 (2016). https://doi.org/10.1109/LED.2016.2574821
Li, W., Liu, H., Wang, S., Chen, S., Yang, Z.: Design of High performance Si/SiGe heterojunction tunneling FETs with a T-shaped gate. Nanoscale Res. Lett. 12(198), 1–8 (2017). https://doi.org/10.1186/s11671-017-1958-3
Chen, S., Liu, H., Wang, S., Li, W., Wang, X., Zhao, L.: Analog/RF performance of T-shape gate dual-source tunnel field-effect transistor. Nanoscale Res. Lett. 13(321), 1–13 (2018). https://doi.org/10.1186/s11671-018-2723-y
Kim, J.H., Kim, H.W., Kim, G., Kim, S., Park, B.-G.: Demonstration of fin-tunnel field-effect transistor with elevated drain. Micromachines 10(30), 1–10 (2019). https://doi.org/10.3390/mi10010030
Vasen, T., Ramvall, P., Afzalian, A., Doornbos, G., Holland, M., Thelander, C., Dick, K.A., Wernersson, L.-E., Passlack, M.: Vertical gate-all-around nanowire GaSb-InAs core-shell n-type tunnel FETs. Sci. Rep. 9(202), 1–9 (2019). https://doi.org/10.1038/s41598-018-36549-z
Hanna, A.N., Fahad, H.M., Hussain, M.M.: InAs/Si hetero-junction nanotube tunnel transistors. Sci. Rep. 5(9843), 1–7 (2015). https://doi.org/10.1038/srep09843
Wang, P.-Y., Tsui, B.-Y.: SixGe1-x epitaxial tunnel layer structure for p-channel tunnel FET improvement. IEEE Trans. Electron Devices 60(12), 4098–4104 (2013). https://doi.org/10.1109/TED.2013.2287633
Anghel, C., Chilagani, P., Amara, A., Vladimirescu, A.: Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric. Appl. Phys. Lett. 96, 122104 (2010). https://doi.org/10.1063/1.3367880
Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007). https://doi.org/10.1109/TED.2007.899389
Kumar, N., Raman, A.: Novel design approach of extended gate-on-source based charge-plasma vertical-nanowire TFET: proposal and extensive analysis. IEEE Trans. Nanotechnol. 19, 421–428 (2020). https://doi.org/10.1109/TNANO.2020.2993565
Solay, L.R., Kumar, N., Amin, S.I., Kumar, P., Anand, S.: Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor. Semicond. Sci. Technol. 37, 115001-1–10 (2022). https://doi.org/10.1088/1361-6641/ac86e9
Saeidi, A., Rosca, T., Memisevic, E., Stolichnov, I., Cavalieri, M., Wernersson, L.-E., Ionescu, A.M.: Nanowire tunnel FET with simultaneously reduced subthermionic subthreshold swing and off-current due to negative capacitance and voltage pinning effects. Nano Lett. 20, 3255–3262 (2020). https://doi.org/10.1021/acs.nanolett.9b05356
Chen, C., Huang, Q., Zhu, J., Wang, Z., Zhao, Y., Jia, R., Guo, L., Huang, R.: New insights into energy efficiency of tunnel FET with awareness of source doping gradient variation. IEEE Trans. Electron Devices 65(5), 2003–2009 (2018). https://doi.org/10.1109/TED.2018.2812828
Chen, Z.X., Yu, H.Y., Singh, N., Shen, N.S., Sayanthan, R.D., Lo, G.Q., Kwong, D.-L.: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett. 30(7), 754–756 (2009). https://doi.org/10.1109/LED.2009.2021079
Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤ 50-mV/decade subthreshold swing. IEEE Electron Device Lett. 32(11), 1504–1506 (2011). https://doi.org/10.1109/LED.2011.2165331
Atlas User’s Manual, (2018) Silvaco Inc., Santa Clara, CA, USA, 10
Liu, K.-M., Cheng, C.-P.: Investigation on the effects of gate-source overlap/underlap and source doping gradient of n-type Si cylindrical gate-all-around tunnel field-effect transistors. IEEE Trans. Nanotechnol. 19, 382–389 (2020). https://doi.org/10.1109/TNANO.2020.2991787
Luong, G.V., Narimani, K., Tiedemann, A.T., Bernardy, P., Trellenkamp, S., Zhao, Q.T., Mantl, S.: Complementary strained Si GAA nanowire TFET inverter with suppressed ambipolarity. IEEE Electron Device Lett. 37(8), 950–953 (2016). https://doi.org/10.1109/LED.2016.2582041
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We thank the National Center for High-performance Computing (NCHC) for providing computational and storage resources.
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Liu, KM., Hsieh, YE. The effects of source doping concentration and doping gradient on the ON-state current of Si nanowire TFETs. J Comput Electron 22, 209–218 (2023). https://doi.org/10.1007/s10825-022-01995-6
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DOI: https://doi.org/10.1007/s10825-022-01995-6