Skip to main content
Log in

Performance Evaluation of 10nm SMG FinFET with Architectural Variation towards DC/RF and Temperature Aspects

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

FinFET structures of 10 nm technology node with promising design enhancements like hybrid spacer, raised source and drain extensions, and silicide interfaces have been analysed and compared. Analog figures of merit like drain current, transconductance, intrinsic gain, and transconductance generation factor are determined here. Furthermore, RF figures of merit like cut-off frequency, intrinsic delay, and gate capacitance are analysed. These parameters have been determined at three different temperatures (200 K, 300 K, 400 K) to study the effect of temperature on device performance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Roy K, Mukhopadhyay S, Meimand HM (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91(2):305–327

    Article  CAS  Google Scholar 

  2. Hisamoto D et al (2000) FinFET-a self-aligned double-gate MOSFET scalable to 20nm. IEEE Trans Electron Dev 47(12):2320–2325

    Article  CAS  Google Scholar 

  3. Colinge J-P et al (2008) FinFETs and other multi-gate transistors. Springer 73

  4. Yang M, Gusev EP, Ieong M, Gluschenkov O, Boyd DC, Chan KK, Kozlowski PM, D’Emic CP, Sicina RM, Jamison PC et al (2003) Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics. IEEE Electron Device Lett 24(5):339–341

    Article  CAS  Google Scholar 

  5. Schuegraf, Klaus F., C. C. King, and Chenming Hu. "Impact of polysilicon depletion in thin oxide MOS technology." 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers. IEEE, 1993

  6. Hyohyun Nam, Changhwan Shin, Jung-Dong Park, “Impact of the Metal-Gate Material Properties in FinFET (Versus FD-SOI MOSFET) on Highκ/Metal-Gate Work-Function Variation”, IEEE Transactions on Electron Devices, Vol. 65, No. 11, 2018

  7. Ko K, Kang M, Jeon J, Shin H (2019) Compact model strategy of metal-gate work-function variation for ultra-scaled finfet and vertical GAA fets. IEEE Trans Electron Devices 66(3):1613–1616

    Article  CAS  Google Scholar 

  8. "10nm Technology - Taiwan Semiconductor Manufacturing Company Limited", Tsmc.com, 2017. [Online]. Available: https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm

  9. Kedzierski J, Meikei Ieong, Nowak E, Kanarsky TS, Ying Zhang, Roy R, Boyd D, Fried D, Wong HSP (2003) Extension and source/drain design for high-performance finFET devices. IEEE Trans Electron Devices 50(4):952–958

    Article  CAS  Google Scholar 

  10. Chauhan YS, Lu DD, Sriramkumar V, Khandelwal S, Duarte JP, Payvadosi N, Niknejad A, Hu C (2015) FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press

  11. Metz MV et al (2008) Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors. U.S. Patent 7:425–500

    Google Scholar 

  12. Intel Corp, "uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors", US7425500B2, 2007

  13. Matsukawa T, Liu Y, Endo K, Tsukada J, Ishikawa Y et al (2012) Variability origins of parasitic resistance in FinFETs with Silicided source/drain. IEEE Electron Device Letters 33(4):474–476

    Article  CAS  Google Scholar 

  14. T. Ando, J. Chang, S. Kanakasabapathy, P. Kulkarni, T. Standaert and T. Yamashita, "FinFET parasitic capacitance reduction using air gap", US 8,637,930 B2, 2014

    Google Scholar 

  15. Sachid AB, Huang Y-M, Chen Y-J, Chen C-C, Lu DD, Chen MC, Hu C (2016) Finfet with encased air-gap spacers for high performance and low-energy circuits. IEEE Electron Device Lett 38(1):16–19

    Article  Google Scholar 

  16. Cheng K et al (2016) "air spacer for 10nm FinFET CMOS and beyond," 2016 IEEE international Electron devices meeting (IEDM). CA, San Francisco, pp 17.1.1–17.1.4

    Book  Google Scholar 

  17. Saha R, Bhowmick B, Baishya S (2018) Comparative analysis among single material gate, double material gate, and triple material gate FinFETs: RF/analog and digital inverter performance. J Nanoelectron Optoelectron 13(6):803–811

    Article  Google Scholar 

  18. R. Chau, B. Doyle, J. Kavalieros, D. Barlage, S. Datta and S. Hareland, "tri-gate devices and methods of fabrication", US 6,858,478 B2, 2005

    Google Scholar 

  19. Barraud, S., Rivallin, P. and Scheiblin, P., Nanowire semiconductor device partially surrounded by a gate. US 9,728.405 B2, 2017

  20. Yu P, Wu J, Liu S, Xiong J, Jagadish C, Wang Z (2016) Design and fabrication of silicon nanowires towards efficient solar cells. Nano Today 11(6):704–737

    Article  CAS  Google Scholar 

  21. Rousseau P, Griffin P, Fang W, Plummer J (1998) Arsenic deactivation enhanced diffusion: A time, temperature, and concentration study. J ApplPhys 84(7):3593–3601. https://doi.org/10.1063/1.368593

    Article  CAS  Google Scholar 

  22. Yoon J-S (2018) Dc performance variations of soi finfets with different silicide thickness. Advan Condensed Matter Phys 2018

  23. Sentaurus Device User Guide, Synopsys, 2016

  24. R. Saha, B. Bhowmick and S. Baishya, "Temperature effect on RF/analog and linearity parameters in DMG FinFET", Appl Physics A, vol. 124, no. 9, 2018

  25. Mohapatra et al (2015) Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics. Superlattices Microstructures 78:134–143

    Article  CAS  Google Scholar 

  26. Mohapatra et al. "ZTC bias point of advanced fin based device: The importance and exploration", Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 3, 2015

  27. Sahu et al (2015) Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges. Mater Sci Semiconductor Process 31:175–183

    Article  CAS  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to S. Routray.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Nikhil, G.P., Dimri, C., Mohanty, P.K. et al. Performance Evaluation of 10nm SMG FinFET with Architectural Variation towards DC/RF and Temperature Aspects. Silicon 13, 2933–2941 (2021). https://doi.org/10.1007/s12633-020-00608-w

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00608-w

Keywords

Navigation