Abstract
Fully Depleted Silicon On Insulator (FDSOI) structures are present-era technology as it has enhanced control over Short Channel Effects in the sub-nanometre regime. This paper studies the analog and radio frequency performance of junctionless FinFET with dual material gate (DMG JLFinFET) based on FDSOI for low power applications. We extracted analog and radio frequency parameters with the variation of fin height (FH = 10 nm to 30 nm) and fin width (FW = 46 nm). The parameters like transconductance (gm), transconductance generation factor, cut-off frequency (fT), intrinsic delay (τ), gate capacitance (Cgg), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), and transconductance frequency product, gain bandwidth product are calculated. At FH = 6 nm all the parameters are increased except time delay which was small decrement. Similarly for FW also all the parameters are improved with increment of fin width except time delay. In contempt Cgd and Cgg are less impact on dimensional variation. From this study it reveals that, in FinFET design, designers have to consider dimensional variations in Anlog/RF parameters and FinFET is suitable candidate for nano scale low power Anlog/RF applications. In this work all these simulations are carried out by Cogenda Visual TCAD.
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J.P. Colinge, C.W. Lee, A. Afzalian et al., Nanowire transistors without junctions. Nat. Nanotechnol. 5, 225–229 (2010). https://doi.org/10.1038/nnano.2010.15
J.P. Duarte, S.J. Choi, M.D.Y.K. IlChoi, Simple analytical bulk current model for long-channel double-gate junctionless transistors. IEEE Electron Device Lett. 32, 704–706 (2011). https://doi.org/10.1109/LED.2011.2127441
J.M. Sallese, N. Chevillon, C. Lallement et al., Charge-based modeling of junctionless double-gate field-effect transistors. IEEE Trans. Electron Devices 58, 2628–2637 (2011). https://doi.org/10.1109/TED.2011.2156413
C. Zhang, W. Choi, P. Mohseni, X. Li, InAs nanowire gate-all-around MOSFETs by heterogeneous planar VLS growth. InAs nanowire gate-all-around MOSFETs by heterogeneous planar VLS growth (2015)
R. Kusuma, V.H.R. Talari (2021) Performance analysis of FinFET using gate stack and workfunction engineering in 14nm technology. In: 2021 2nd International conference for emerging technology (INCET), Belagavi, India, pp 1–4. https://doi.org/10.1109/INCET51464.2021.9456268
G. Katti, N. DasGupta, A. DasGupta, Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution OF 3-D poisson’s equation. IEEE Trans. Electron Devices 51, 1169–1177 (2004). https://doi.org/10.1109/TED.2004.830648
V. Narendar, P. Narware, V. Bheemudu, B. Sunitha, Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET. SILICON 12, 2283–2291 (2020). https://doi.org/10.1007/s12633-019-00322-2
H.S.P. Wong, K.K. Chan, Y. Taur, Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. In: Technical digest—international electron devices meeting, IEDM. pp 427–430 (1997)
G. Pei, J. Kedzierski, P. Oldiges et al., FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans. Electron Devices 49, 1411–1419 (2002). https://doi.org/10.1109/TED.2002.801263
S.S. Mahato, P. Chakraborty, T.K. Maiti et al., DIBL in short-channel strained-Si n-MOSFET
E. Yu, K. Heo, S. Cho, Characterization and optimization of inverted-T FinFET under nanoscale dimensions. IEEE Trans. Electron Devices 65, 3521–3527 (2018). https://doi.org/10.1109/TED.2018.2846478
D. Gola, B. Singh, P.K. Tiwari, subthreshold characteristic analysis and models for Tri-Gate SOI MOSFETs using substrate bias induced effects. IEEE Trans. Nanotechnol. 18, 329–335 (2019). https://doi.org/10.1109/TNANO.2019.2906567
P. Wang, Y. Zhuang, C. Li et al., Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack. Jpn. J. Appl. Phys., 53 (2014). https://doi.org/10.7567/JJAP.53.084201
V. Narendar, Performance enhancement of FinFET devices with gate-stack (GS) high-K dielectrics for nanoscale applications. SILICON 10, 2419–2429 (2018). https://doi.org/10.1007/s12633-018-9774-7
J.P. Colinge, Problems and issues in SOI CMOS technology. In: 1991 IEEE international SOI conference proceedings. Publ by IEEE, pp 126–127 (1992)
S. Veeraraghavan, J.G. Fossum, Short-channel effects in Soi Mosfet’s. IEEE Trans. Electron Devices 36, 522–528 (1989). https://doi.org/10.1109/16.19963
C.K. Pandey, D. Dash, S. Chaudhury, Improvement in analog/RF performances of SOI TFET using dielectric pocket. Int. J. Electron. 107, 1844–1860 (2020). https://doi.org/10.1080/00207217.2020.1756439
R.H. Yan, A. Ourmazd, K.F. Lee, Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1704–1710 (1992). https://doi.org/10.1109/16.141237
H.S. Wong, D.J. Frank, Y. Taur, J.M.C. Stork, Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs. In: Technical Digest—International Electron Devices Meeting. IEEE, pp 747–750 (1994)
B. Bhowmick, S. Baishya, GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter (2018)
A. Chaudhry, M.J. Kumar, Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET. IEEE Trans. Electron Devices 51, 1463–1467 (2004). https://doi.org/10.1109/TED.2004.833961
A. Kranti, T.M. Chung, D. Flandre, J.P. Raskin, Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications. Solid State Electron. 48, 947–959 (2004). https://doi.org/10.1016/j.sse.2003.12.014
S. Datta, G. Dewey, M. Doczy et al., High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack. In: IEEE International Electron Devices Meeting 2003 28.1.1–28.1.4 (2003). https://doi.org/10.1109/IEDM.2003.1269365
S. Tripathi, V. Narendar, A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET. Superlattices Microstruct. 83, 476–487 (2015). https://doi.org/10.1016/j.spmi.2015.03.048
A.B. Sachid, C.R. Manoj, D.K. Sharma, V.R. Rao, Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Device Lett. 29, 128–130 (2008). https://doi.org/10.1109/LED.2007.911974
V. Narendar, R.A. Mishra, Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattices Microstruct. 85, 357–369 (2015). https://doi.org/10.1016/j.spmi.2015.06.004
C.W. Lee, A. Afzalian, N.D. Akhavan et al., Junctionless multigate field-effect transistor. Appl. Phys. Lett., 94 (2009). https://doi.org/10.1063/1.3079411
J.P. Colinge, C.W. Lee, N. Dehdashti Akhavan et al., Junctionless transistors: physics and properties. In: Engineering Materials. Springer Science and Business Media B.V., pp 187–200 (2011)
F. Chen, X. Bin, C. Hella et al., A study of mixtures of HfO2 and TiO2 as high-k gate dielectrics. Microelectronic Eng., pp 263–266 (2004)
J.P. Raskin, T.M. Chung, V. Kilchytska et al., Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization. IEEE Trans. Electron Devices 53, 1088–1095 (2006). https://doi.org/10.1109/TED.2006.871876
R. Kusuma, V.K.H.R. Talari, Design and optimization of dual material gate junctionless FinFET using dimensional effect, gate oxide and workfunction engineering at 7 nm technology node. SILICON (2022). https://doi.org/10.1007/s12633-022-01769-6
J.P. Raskin, G. Pailloncy, D. Lederer et al., High-frequency noise performance of 60-nm gate-length FinFETs. IEEE Trans. Electron Devices 55, 2718–2727 (2008). https://doi.org/10.1109/TED.2008.2003097
G. Crupi, D.M.M.P. Schreurs, A. Caddemi et al., Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects. Microelectron. Eng. 86, 2283–2289 (2009). https://doi.org/10.1016/j.mee.2009.04.006
G. Crupi, A. Caddemi, D.M.M.P. Schreurs et al., Microwave noise modeling of FinFETs. Solid-State Electron. 56, 18–22 (2011). https://doi.org/10.1016/j.sse.2010.10.010
Semiconductor Industry Association (2016) International Technology Roadmap for Semiconductors, 2015 Results. Itrpv., pp. 1–37
Cogenda Pvt. Ltd., Genius Semiconductor Device Simulator Reference Manual. Singapore (2008)
B. Yu, L. Chang, S. Ahmed et al., FinFET scaling to 10nm gate length. In: Digest International Electron Devices Meeting, pp 251–254 (2002). https://doi.org/10.1109/IEDM.2002.1175825
R. Saha, B. Bhowmick, S. Baishya, Impact of work function on analog/RF and linearity parameters in step-FinFET. Indian JPhys 95, 2387–2392 (2021). https://doi.org/10.1007/s12648-020-01895-0
R. Saha, B. Bhowmick, S. Baishya, Impact of lateral straggle on linearity performance in gate-modulated (GM) TFET. Appl. Phys. A Mater. Sci. Process., p. 126 (2020). https://doi.org/10.1007/S00339-020-3373-3
J.-P. Raskin et al., High-frequency noise performance of 60-nm gate-length FinFETs. IEEE Trans. Electron Devices 55(10), 2718–2727 (2008). https://doi.org/10.1109/TED.2008.2003097
S. Sahay, M.J. Kumar, Insight into lateral band-to-band-tunneling in nanowire junctionless FETs. IEEE Trans. Electron Devices 63(10), 4138–4142 (2016). https://doi.org/10.1109/TED.2016.2601239
V.B. Sreenivasulu, V. Narendar, A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length. SILICON (2021). https://doi.org/10.1007/s12633-021-00987-8
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The authors thank to the Department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.
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RK: Writing—Original draft preparation, Formal Analysis, Investigation, Simulation, and Data Curation. VKHRT: Conceptualization, Methodology, Supervision.
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Kusuma, R., Talari, V.K.H.R. Dimensional Effect on Analog/RF Performance of Dual Material Gate Junctionless FinFET at 7 nm Technology Node. Trans. Electr. Electron. Mater. 24, 178–187 (2023). https://doi.org/10.1007/s42341-023-00440-0
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DOI: https://doi.org/10.1007/s42341-023-00440-0