Abstract
In this paper, 2-D analytical models of channel central potential, threshold voltage, subthreshold current and subthreshold swing for graded channel double gate (GC-DG) Junctionless FETs (JLFETs) have been presented. The 2-D Poisson’s equation has been solved to determine the channel central potential by parabolic approximation method with appropriate boundary conditions. The minimum potential for the channel is obtained from the channel potential expression in order to formulate threshold voltage, subthreshold current and subthreshold swing. The validity of the model results has been verified using TCAD numerical data obtained from 2-D ATLAS device simulator from Silvaco.
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Colinge J-P, Lee C-W, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229. https://doi.org/10.1038/nnano.2010.15
Lee C, Afzalian A, Akhavan ND et al (2009) Junctionless multigate field-effect transistor Junctionless multigate field-effect transistor. Appl Phys Lett 94:053511. https://doi.org/10.1063/1.3079411
Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R, Dehdashti Akhavan N, Razavi P (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65–66:33–37. https://doi.org/10.1016/j.sse.2011.06.004
Gola D, Singh B, Tiwari PK (2017) A threshold voltage model of tri-gate Junctionless field-effect transistors including substrate Bias effects. IEEE Trans Electron Devices 64:3534–3540
Gola D, Singh B, Tiwari PK (2018) Subthreshold modeling of tri-gate Junctionless transistors with Variable Channel edges and substrate Bias effects. IEEE Trans Electron Devices 65:1663–1671. https://doi.org/10.1109/TED.2018.2809865
Chiang T-K (2012) A quasi-two-dimensional threshold voltage model for Short-Channel Junctionless. IEEE Trans Electron Devices 59:2284–2289. https://doi.org/10.1109/TED.2012.2202119
Gnudi A, Reggiani S, Gnani E, Baccarani G (2013) Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Trans Electron Devices 60:1342–1348. https://doi.org/10.1109/TED.2013.2247765
Jin X, Liu X, Kwon HI, Lee JH, Lee JH (2013) A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid State Electron 82:77–81. https://doi.org/10.1016/j.sse.2013.02.004
Wang P, Zhuang Y, Li C, Li Y, Jiang Z (2014) Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack. Jpn J Appl Phys 53:084201. https://doi.org/10.7567/JJAP.53.084201
Agrawal AK, Koutilya PNVR, Jagadesh Kumar M (2015) A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor. J Comput Electron 14:686–693. https://doi.org/10.1007/s10825-015-0710-4
Kumari V, Modi N, Saxena M, Member S (2015) Theoretical investigation of dual material Junctionless double gate transistor for analog and digital performance. IEEE Trans Electron Devices 62:2098–2105. https://doi.org/10.1109/TED.2015.2433951
Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S (2016) Analytical modeling of channel potential and threshold voltage of double-gate Junctionless FETs with a vertical Gaussian-like doping profile. IEEE Trans Electron Devices 63:2299–2305. https://doi.org/10.1109/TED.2016.2556227
Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S (2017) Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors. Mater Sci Semicond Process 58:82–88. https://doi.org/10.1016/j.mssp.2016.10.051
Kumari V, Kumar A, Saxena M, Member S (2018) Empirical model for nonuniformly doped symmetric double-gate Junctionless transistor. IEEE Trans Electron Devices 65:314–321. https://doi.org/10.1109/TED.2017.2776607
Kumari V, Kumar A, Saxena M, Gupta M (2018) Superlattices and microstructures study of Gaussian doped double gate JunctionLess ( GD-DG- JL ) transistor including source drain depletion length : model for sub-threshold behavior. Superlattice Microst 113:57–70. https://doi.org/10.1016/j.spmi.2017.09.049
Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D analytical modeling of threshold voltage for Graded-Channel dual-material double-gate MOSFETs. IEEE Trans Electron Devices 63:966–973. https://doi.org/10.1109/TED.2016.2520096
Goel E, Kumar S, Singh B, Singh K, Jit S (2017) Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs. Superlattice Microst 106:147–155. https://doi.org/10.1016/j.spmi.2017.03.047
Chen Y, Mohamed M, Jo M, Ravaioli U, Xu R (2013) Junctionless MOSFETs with laterally graded-doping channel for analog / RF applications. J Comput Electron 12:757–764. https://doi.org/10.1007/s10825-013-0478-3
Irradiation H, Munteanu D, Autran J, Member S (2012) 3-D numerical simulation of bipolar Ampli fi cation in Junctionless double-gate MOSFETs under. IEEE Trans Nucl Sci 59:773–780
Wang Y, Shan C, Liu C, Li XJ, Yang JQ, Tang Y, Bao MT, Cao F (2017) Graded-channel junctionless dual-gate MOSFETs for radiation tolerance. Jpn J Appl Phys 56:124201. https://doi.org/10.7567/JJAP.56.124201
Ferhati H, Djeffal F (2018) Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications. J Comput Electron 17:129–137. https://doi.org/10.1007/s10825-017-1052-1
Atlas (2016) A 2-D Device Simulator. Silvaco international, Santa Clara
Choi SJ, Il MD, Kim S et al (2011) Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett 32:125–127. https://doi.org/10.1109/LED.2010.2093506
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Duksh, Y.S., Singh, B., Gola, D. et al. Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs. Silicon 13, 1231–1238 (2021). https://doi.org/10.1007/s12633-020-00514-1
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DOI: https://doi.org/10.1007/s12633-020-00514-1