Abstract
Junctionless Metal Oxide Semiconductor Field-Effect Transistor (JL MOSFET) is one of the promising candidate to replace the junction based MOSFET for upcoming technology nodes. Semiconductor industries are continuously urging for large ON current with the low OFF current and low specific on resistance. However, high ON current is achieved in Conventional (Conv.) JL DG MOSFET by using high doping concentration at the cost of high OFF current which leads depletion mode operation. Moreover, low doping, narrow channel thickness and high work function gate materials are using to operate Conv. JL DG MOSFET in enhancement mode (Vth > 0 V for N-JL DG MOSFET, Vth < 0 V for P-JL DG MOSFET) but ON current is reduced in all above mentioned solutions. To overcome the above mentioned problems, a new architecture is developed called Recessed JL DG MOSFET. In Recessed JL DG MOSFET silicon region is recessed under the gate region and some gate portion is extended towards source and drain region. Recessed JL DG MOSFET shows the same ON current as achieved in Conv. JL DG MOSFET with very low OFF current (leakage current) by considering high doping concentration. Surface potential, electron density, energy band distribution, drain current have been investigated to proof the enhancement mode operation of Recessed JL DG MOSFET. Figure of Merits (FOMs) for RF performance such as Trans-conductance, capacitance and intrinsic power gain (S21), Trans-conductance frequency product (TFP), Gain frequency product (GFP) and Gain trans-conductance frequency product (GTFP) have also investigated of Recessed JL DG MOSFET.
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References
Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'neill B, Blake A, White M, Kelleher AM (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225
Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP (2010) High-temperature performance of silicon junctionless MOSFETs. IEEE Trans Electron Devices 57(3):620–625
Jin X, Liu X, Wu M, Chuai R, Lee JH, Lee JH (2013) A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structures. Solid State Electron 79:206–209
Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511
Sorée B, Magnus W, Pourtois G (2008) Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode. J Comput Electron 7(3):380–383
Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Nazarov AN, Doria RT (2010) Reduced electric field in junctionless transistors. Appl Phys Lett 96(7):073510
Wen SM, Chui CO (2013) CMOS junctionless field-effect transistors manufacturing cost evaluation. IEEE Trans Semicond Manuf 26:162–168
Veloso A, Hellings G, Cho MJ, Simoen E, Devriendt K, Paraschiv V, Vecchio E, Tao Z, Versluijs JJ, Souriau L, Dekkers H (2015) Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS. In 2015 symposium on VLSI technology (VLSI technology):T138-T139
Colinge JP, Lee CW, Akhavan ND, Yan R, Ferain I, Razavi P, Yu R (2011) Junctionless transistors: physics and properties. In Semiconductor-On-Insulator Materials for Nanoelectronics Applications: 187–200
Lim BS, Arshad MM, Othman N, Fathil MFM, Fatin MF, Hashim U (2014) The impact of channel doping in junctionless field effect transistor. In 2014 IEEE international conference on semiconductor electronics (ICSE2014):112-114
Duarte JP, Choi SJ, Moon DI, Choi YK (2011) Simple analytical bulk current model for long-channel double-gate junctionless transistors. IEEE Electron Device Lett 32(6):704–706
Lou H, Zhang L, Zhu Y, Lin X, Yang S, He J, Chan M (2012) A junctionless nanowire transistor with a dual-material gate. IEEE Trans Electron Devices 59(7):1829–1836
Kadotani N, Ohashi T, Takahashi T, Oda S, Uchida K (2011) Experimental study on electron mobility in accumulation-mode silicon-on-insulator metal–oxide–semiconductor field-effect transistors. Jpn J Appl Phys 50(9R):094101
TCAD (2018) Sentaurus device user manual. Synopsys, CA
Sharma D, Vishvakarma SK (2015) Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron J 46(8):731–739
Kranti A, Armstrong GA (2010) Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Transactions on Circuits and Systems I 57:3048–3054
Acknowledgments
Author would like to thank Advanced Nanoelectronic Device & Circuit Research Group, Indian Institute of Science, Bangalore, and Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi to use their resources and support.
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Ajay Investigation of Recessed Junctionless Double Gate MOSFET for Radio Frequency Applications. Silicon 12, 2799–2807 (2020). https://doi.org/10.1007/s12633-020-00378-5
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DOI: https://doi.org/10.1007/s12633-020-00378-5