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Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET

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Abstract

In this paper, we examine the impact of variation in the lateral straggle parameter on linearity and reliability performance for the Hetero-stacked TFET. By incorporating hetero-stack in the Source, both the subthreshold as well as the drain current can be improved. Although the tunnel field effect transistor is considered a valid candidate to replace the MOSFET for low power applications, the device performance depends on the precision in the fabrication process. During fabrication process, ion implantation technique is used to realize the variation in the tilt angle. This variation causes an extension of dopants from the regions of source and drain to the channel, which significantly affects the performance of the device. The linearity and reliability performances of the Hetero-stacked TFET (HS-TFET) are analyzed by varying the lateral straggle parameter (σ) from 0 to 8 nm. A higher value of the lateral straggling parameter causes an increase in the on current due to the enhanced electron tunneling rate. However, linearity performance tends to deteriorate as the lateral straggle parameter increases. The linearity and reliability of the device are studied in terms of transconductances of higher order (gm2 and gm3), VIP2, VIP3, IIP3, IMD3 and 1-dB compression point.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam, 788010, India

    K. Vanlalawmpuia & Brinda Bhowmick

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  1. K. Vanlalawmpuia
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  2. Brinda Bhowmick
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Correspondence to K. Vanlalawmpuia.

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Vanlalawmpuia, K., Bhowmick, B. Linearity Performance Analysis Due to Lateral Straggle Variation in Hetero-Stacked TFET. Silicon 12, 955–961 (2020). https://doi.org/10.1007/s12633-019-00189-3

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