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Lateral Straggle Parameter and Its Impact on Hetero-Stacked Source Tunnel FET

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Contemporary Trends in Semiconductor Devices

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 850))

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Abstract

The strict power restrictions of integrated circuits and the non-scalability of the subthreshold slope in a metal-oxide semiconductor field-effect transistor (MOSFET) present major challenges to the continuous scaling of field-effect transistors. Henceforth, tunnel field-effect transistors (Tunnel FETs) have been deemed an optimistic contender to substitute the well-known conventional MOSFET as they possess a steep subthreshold slope lower than 60 mV/decade along with its fast switching characteristics at a low operating power supply voltage. Despite numerous advantages, the performance of the tunnel FET primarily relies on the accuracy in the manufacturing procedure. Ion implantation techniques have been employed to comprehend the variations in non-zero tilting angle. This extends the dopants from the source as well as drain regions into the channel region and affects the performances of tunnel FET significantly. Using Technology Computer Aided Design (TCAD) simulations, detailed examination on the impact of variations in lateral straggling parameters (σ) for a hetero-stacked source tunnel FET (HSS-TFET) is carried out. The chapter focuses on the investigation of Analog/RF figure of merits of the HSS-TFET due to lateral straggling variations. A mixed-mode HSS-tunnel FET is analyzed by the implementation of a digital HSS-tunnel FET inverter for variations in the straggling parameter.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India

    K. Vanlalawmpuia & Brinda Bhowmick

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  1. K. Vanlalawmpuia
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  2. Brinda Bhowmick
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Editors and Affiliations

  1. Department of Electronics and Communication Engineering, Tezpur University, Napaam, Assam, India

    Rupam Goswami

  2. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur, Rajasthan, India

    Rajesh Saha

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Vanlalawmpuia, K., Bhowmick, B. (2022). Lateral Straggle Parameter and Its Impact on Hetero-Stacked Source Tunnel FET. In: Goswami, R., Saha, R. (eds) Contemporary Trends in Semiconductor Devices. Lecture Notes in Electrical Engineering, vol 850. Springer, Singapore. https://doi.org/10.1007/978-981-16-9124-9_8

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  • DOI: https://doi.org/10.1007/978-981-16-9124-9_8

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