Abstract
In this work, we propose for the first time statistical driving current and input capacitance model of MOSFET for high speed CMOS circuit applications. The proposed model is based on Berkeley Short-channel IGFET Model BSIM4v4.7. Rather than considering few parameters variations our algorithm considers all process parameters and environment parameters variations. The accuracy of the model was verified with Monte Carlo analysis for 32nm technology. The model shows better accuracy. The propagation delay of logic gates are calculated by using driving current and input capacitance of logic gates. Hence we proposed our MOSFET model to calculate the propagation delay of the logic gates. The validity of model is also verified for temperature and power supply variations. Finally, it is shown that the model can accurately predict the drain current and input capacitance of the MOSFET.
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Patil, S.R., Gautam, D.K. Statistical Drain Current and Input Capacitance of MOSFET Model for High Speed CMOS Circuits Application. Silicon 8, 25–31 (2016). https://doi.org/10.1007/s12633-015-9284-9
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DOI: https://doi.org/10.1007/s12633-015-9284-9