Abstract
In this paper, a new open source floating-gate MOSFET (FGMOSFET) device-level micro-model to facilitate accurate analog circuit design is presented. The floating gate is charged by the Fowler–Nordheim tunneling effect. The equations representing the new device model were explored and verified on MATLAB. Subsequently, Verilog-A script was employed to combine the equations and build the complete device model. The new FGMOSFET circuit model was plugged-in as a pop-up menu component in a standard 130 nm CMOS technology design library. Thus, it can be instanced directly on a schematic editor palette for analog circuit simulation and design in a similar fashion as the standard MOSFET devices.
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References
Rodriguez-Villegas, E., & Barnes, H. (2003). Solution to trapped charge in FGMOS transistors. IET Electronics Letters, 39(19), 1416–1417.
Hasler, P., Minch, B. A., & Diorio, C. (1999). Adaptive circuits using pFET floating-gate devices. In Proceedings 20th anniversary IEEE conference on advanced research in VLSI (pp. 215–231).
Ochoa-Padilla, J. L., Gomez-Castañeda, F., & Moreno-Cadenas, J. A. (2013). Floating-gate MOS charge programming using pulsed hot-electron injection. In Proceedings 2013 IEEE 10th international conference on electrical engineering, computing science and automatic control (CCE) (pp. 478–481).
Basu, A., & P. Hasler. (2007). A fully integrated architecture for fast programming of floating gates. In Proceedings 2007 IEEE international symposium on circuits and systems (ISCAS 2007) (pp. 957–960).
Compagnoni, C. M., Ielmini, D., Spinelli, A. S., & Lacaita, A. L. (2005). Modeling of tunneling P/E for nanocrystal memories. IEEE Transactions on Electron Devices, 52(4), 569–576.
Pavan, P., Larcher, L., Cuozzo, M., Zuliani, P., & Conte, A. (2003). A complete model of E/sup 2/PROM memory cells for circuit simulations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(8), 1072–1079.
Scheick, L. Z., McNulty, P. J., & Roth, D. R. (2000). Measurement of the effective sensitive volume of FAMOS cells of an ultraviolet erasable programmable read-only memory. IEEE Transactions on Nuclear Science, 47(6), 2428–2434.
Rapp, S. J., Mcmillan, K. R., & Graham, D. W. (2011). SPICE-compatible modelling technique for simulating floating-gate transistors. Electronics Letters, 47(8), 483–485.
Rahimi, K., Diorio, C., Hernandez, C., Brockhausen, M. D. (2002). A simulation model for floating-gate MOS synapse transistors. In IEEE international symposium on proc. circuits and systems, 2002, ISCAS 2002 (Vol. 2, pp. II–II). IEEE.
Yin, L., Embabi, S. H. K., & Sanchez-Sinencio, E. (1997). A floating-gate mosfet D/A converter. In IEEE international symposium on circuits and systems, 1997. ISCAS 1997 (Vol. 1, pp. 409–412). IEEE.
Angelov, G., Panayotov, I., & Hristov, M. (2008). EKV MOSFET model implementation in Matlab and Verilog-A. In Proceedings 26th IEEE international conference on microelectronics (pp. 515–518).
Zhou, Y., Li, Y., Wang, B. (2016). Spice modeling of 4H-SiC MOSFET based on the advanced mobility model. In Proceedings 2016 IEEE 4th workshop on wide bandgap power devices and applications (pp. 1–7).
Thomsen, A., & Brooke, M. A. (1991). A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process. IEEE Electron Device Letters, 12(3), 111–113.
Cullinan, M. (2015). Equation defined device modelling of floating gate MOSFETs”. Doctoral dissertation, London Metropolitan University. http://repository.londonmet.ac.uk/960/.
Jeon, J., et al. (2012). Accurate compact modeling for sub-20-nm nand flash cell array simulation using the PSP model. IEEE Transactions on Electron Devices, 59(12), 3503–3509.
Li, J., & Hasan, R. (2014). An inductive-degenerated current-bleeding LNA-merged CMOS mixer for 866 MHz RFID reader. Analog Integrated Circuits and Signal Processing-An International Journal, 80(2), 173–185.
Li, J., Joshi, S., Barnes, R., & Rosenbaum, E. (2006). Compact modeling of on-chip ESD protection devices using Verilog-A. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(6), 1047–1063.
Wang, X., Xu, B., & Chen, L. (2017). Efficient memristor model implementation for simulation and application. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(7), 1226–1230.
Manku, T., & Heasell, E. L. (1992). An analytical model for floating-gate MOSFET including the effects of the overlapping capacitance. IEEE Transactions on Electron Devices, 39(12), 2821–2823.
Larcher, L., Pavan, P., Albani, L., & Ghilardi, T. (2001). Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells. IEEE Transactions on Electron Devices, 48(9), 2081–2089.
Larcher, L., Pavan, P., Pietri, S., Albani, L., & Marmiroli, A. (2002). A new compact DC model of floating gate memory cells without capacitive coupling coefficients. IEEE Transactions on Electron Devices, 49(2), 301–307.
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Appendix
Appendix
The key Verilog-A code of the proposed open source FGMOSFET model.
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Zhang, C., Hasan, S.M.R. A new floating-gate MOSFET model for analog circuit simulation and design. Analog Integr Circ Sig Process 101, 1–11 (2019). https://doi.org/10.1007/s10470-018-1374-3
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DOI: https://doi.org/10.1007/s10470-018-1374-3