Abstract
A fault-tolerant spaceborne mass memory architecture is presented based on entirely commercial-off-theshelf components. The highly modularized and scalable memory kernel supports the hierarchical design and is well suited to redundancy structure. Error correcting code (ECC) and periodical scrubbing are used to deal with bit errors induced by single event upset. For 8-bit wide devices, the parallel Reed Solomon(10, 8) can perform coder/decoder calculations in one clock cycle, achieving a data rate of several Gb/s. In space environment, ECC combined with periodical scrubbing is appropriate and it reduces the word error rate by 5 orders of magnitude with 1% timing overhead and small hardware expenditure.
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Supported by Innovative Program of Chinese Academy of Sciences (No. KGCY-SYW-407-02) and Grand International Cooperation Foundation of Shanghai Science and Technology Commission (No. 052207046).
ZHANG Yuning, born in 1981, male, Dr.
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Zhang, Y., Chang, L., Yang, G. et al. Fault-tolerant design of spaceborne mass memory system. Trans. Tianjin Univ. 16, 17–21 (2010). https://doi.org/10.1007/s12209-010-0004-7
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DOI: https://doi.org/10.1007/s12209-010-0004-7