Skip to main content
Log in

Analytical modelling of electrical parameters and the analogue performance of cylindrical gate-all-around FinFET

  • Published:
Pramana Aims and scope Submit manuscript

Abstract

This paper presents the cylindrical gate-all-around (GAA) silicon on insulator (SOI) FinFET, which not only eliminates the corner effect but also shows high on-drain current (\(I_{\mathrm{ON}}\)) (\(\sim \!\!10^{-2}~\mathrm{A}\)), low leakage current (\(I_{\mathrm{OFF}}\)) (\( \sim \!\!10^{-10}~\mathrm{A}\)), high \(I_{\mathrm{ON}}\) \(/\) \(I_{\mathrm{OFF}}\) (\(10^{8}>10^{6}\)) and reduced subthreshold swing (SS) (64.55 mV / dec, which is nearest to the Boltzmann limit of 60 mV / dec). To have a better understanding of the working principles, analytical modelling of electrical parameters such as surface potential, threshold voltage, drain current and SS has been carried out by solving two-dimensional Poisson’s equation using superposition principle. The behaviour of threshold voltage, drain current and SS has been investigated for different dimensional and electrical parameters such as channel lengths, channel radius, gate work functions, dielectric constants, drain-to-source voltages and channel concentrations. The physics-based models have been cross-examined with extracted three-dimensional TCAD simulation results. The modelled values show good agreement with the simulated data. Moreover, analogue performances such as transconductance, output conductance, intrinsic gain and gate capacitance for different channel lengths and radii of the presented device are also studied.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19

Similar content being viewed by others

References

  1. D Hisamoto, W-C Lee, J Kedzierski, H Takeuchi, K Asano, C Kuo, E Anderson, T-J King, J Bokor and C Hu, IEEE Trans. Electron Devices 47, 2320 (2000)

    Article  ADS  Google Scholar 

  2. A Datta, A Goel, R T Cakici, H Mahmoodi, D Lekshmanan and K Roy, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26, 1957 (2007)

    Article  Google Scholar 

  3. S L Tripathi, R Mishra and R A Mishra, 2nd International Conference on Power, Control and Embedded Systems (2012) Vol. 1, p. 1

  4. G Pei, J Kedzierski, P Oldiges, M Ieong and E C C Kan, IEEE Trans. Electron Devices 49, 1411 (2002)

    Article  ADS  Google Scholar 

  5. D Bhattacharya and N K Jha, Adv. Electron. 2014, 1 (2014)

    Article  Google Scholar 

  6. B Yu, L Chang, S Ahmed, H Wang, S Bell, C Y Yang, C Tabery, C Ho, Q Xiang, T-J King, J Bokor, C Hu, M-R Lin and D Kyser, International Electron Devices Meeting (2002) Vol. 251

  7. M A Pavanello, J A Martino, E Simoen, R Rooyackers, N Collaert and C Claeys, Solid State Electron. 51, 285 (2007)

    Article  ADS  Google Scholar 

  8. T Rudenko, V Kilchytska, N Collaert, M Jurczak, A Nazarov and D Flandre, IEEE Trans. Electron Devices 55, 3532 (2008)

    Article  ADS  Google Scholar 

  9. R Das, R Goswami and S Baishya, Superlatt. Microstruct. 91, 51 (2016)

    Article  ADS  Google Scholar 

  10. V Narendar and R A Mishra, Superlatt. Microstruct. 85, 357 (2015)

    Article  ADS  Google Scholar 

  11. M D Ko, C W Sohn, C K Baek and Y H Jeong, IEEE Trans. Electron Devices 60, 2721 (2013)

    Article  ADS  Google Scholar 

  12. K Wu, W W Ding and M H Chiang, International Conference on Simulation of Semiconductor Process and Devices (2013) Vol. 143

  13. Y Li, H M Chou and J W Lee, IEEE Trans. Nanotechnol. 4, 510 (2005)

    Article  ADS  Google Scholar 

  14. B Lakshmi and R Srinivasan, Int. J. Numer. Modell. 30, 1 (2016)

  15. C Chang, J Lin, P Lin, H Hsu, C Chang, M Shih, S Tseng and M Lin, Int. J. Math. Comput. Phys. Electr. Comput. Eng. 7, 333 (2013)

    Google Scholar 

  16. A Burenkov and J Lorenz, 33rd Conference on European Solid-State Device Research (2003) Vol. 3

  17. M Poljak, V Jovanovic and T Suligoj, Microelectron. Eng. 87, 192 (2010)

    Article  Google Scholar 

  18. M Stadele, R J Luyken, M Roosz, M Specht, W Rosner, L Dreeskornfeld, J Hartwich, F Hofmann, J Kretz, E Landgraf and L Risch, Proceedings of 34th European Solid-State Device Research Conference (2004) Vol. 165

  19. M Bhole, A Kurude and S Pawar, Int. J. Eng. Sci. Res. Technol. 2, 2 (2013)

    Google Scholar 

  20. Sentaurus Device User, Synopsys, 2009 (2009)

  21. K V Ramanan and R K Gupta, Electron. Lett. 7, 221 (1971)

    Article  Google Scholar 

  22. B Ray and S Mahapatra, IEEE Trans. Electron Devices 55, 2409 (2008)

    Article  ADS  Google Scholar 

  23. H A Hamid, B Iñíguez and J R Guitart, IEEE Trans. Electron Devices 54, 572 (2007)

    Article  ADS  Google Scholar 

  24. Q Chen, B Agrawal and J D Meindl, IEEE Trans. Electron Devices 49, 1086 (2002)

    Article  ADS  Google Scholar 

  25. Q Chen, E M Harrell and J D Meindl, IEEE Trans. Electron Devices 50, 1631 (2003)

    Article  ADS  Google Scholar 

  26. Y Chen and J Luo, Technical Proceedings, 2001 International Conference on Modeling and Simulation of Microsystems (2001) Vol. 1, p. 546

  27. A Kranti, S Haldar and R S Gupta, Microelectron. J. 32, 305 (2001)

    Article  Google Scholar 

  28. Y Tsividis and C McAndrew, Operation and modeling of the MOS transistor, 3rd edn (McGraw-Hill, NewYork, 2011) p. 212

    Google Scholar 

  29. Y Pratap, P Ghosh, S Haldar, R S Gupta and M Gupta, Microelectron. J. 45, 408 (2014)

    Article  Google Scholar 

  30. J Widiez, F Dauge, T Poiroux, B Previtali, M Mouis and S Deleonibus, 2004 IEEE International SOI Conference (2004) Vol. 185

  31. P Dutta, B Syamal, K Koley, A Dutta and C K Sarkar, Pramana – J. Phys. 89:33 (2017)

    Article  ADS  Google Scholar 

  32. B Yang, K D Buddharaju, S H G Teo, N Singh, G Q Lo and D L Kwong, IEEE Electron Devices Lett. 29, 791 (2008)

    Article  ADS  Google Scholar 

  33. B Jena, K P Pradhan, S Dash, G P Mishra, P K Sahu and S K Mohapatra, Adv. Natural Sci.: Nanosci. Nanotechnol. 6, 035010 (2015)

    ADS  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rajashree Das.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Das, R., Baishya, S. Analytical modelling of electrical parameters and the analogue performance of cylindrical gate-all-around FinFET. Pramana - J Phys 92, 2 (2019). https://doi.org/10.1007/s12043-018-1663-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s12043-018-1663-5

Keywords

PACS Nos

Navigation