Abstract
This article proposes a detailed investigation of the dependence of mobility on source (S)/drain (D) doping concentrations, temperature and interface traps in two architectures of gate-all-around (GAA) FinFETs. Single core gate-all-around (SC-GAA) and dual core S/D gate-all-around (DC-GAA) FinFETs are considered with four cases of mobility in the technology computer-aided design (TCAD) simulation based investigation. A sensitivity parameter in terms of drain current is defined to assess the deviation of the models under examination from reference models. The constant mobility model is used as a reference mobility model to compute the sensitivity for Masetti and Philips unified mobility models. On the other hand, for Masetti and Philips unified mobility models accompanied by high field saturation and mobility degradation (E-normal) model, the devices with high field saturation and mobility degradation (E-normal) model are used as reference. The impact of interface traps on the device performance is reported for the four cases of mobility through the sensitivity parameter. Both acceptor-like and donor-like interface traps are considered at the oxide–semiconductor interface having Gaussian distribution. The sensitivity is reported for peak energy position and trap concentration for the four cases of mobility.
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References
Clarke P (2006) KAIST claims record size 3-nm FinFETs, March14, 2006. www.eetimes.com/document.asp?doc_id=1160025
Das D, Pandey CK (2023) Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET. Microelectron Reliab 146:115024. https://doi.org/10.1016/j.microrel.2023.115024
Das RR, Maity S, Chowdhury A, Chakraborty A, Mitra SK (2022) Effect of positive/negative interface trap charges on the performance of Multi Fin FinFET (M-FinFET). SILICON 14(14):8557–8566. https://doi.org/10.1007/s12633-022-01669-9
Das PS, Deb D, Goswami R, Sharma S, Saha R, Choudhury H (2023) A dual core S/D source/drain GAA FinFET. Tecnología Marcha J 36(6):5–11. https://doi.org/10.18845/tm.v36i6.6748
Das PS, Deb D, Goswami R, Sharma S, Saha R (2024) Fin core dimensionality and corner effect in dual core gate-all-around FinFET. Microelectron J 143:105985. https://doi.org/10.1016/j.mejo.2023.105985
Deb D, Goswami R, Baruah RK, Kandpal K, Saha R (2022) Parametric investigation and trap sensitivity of npn double gate TFETs. Comput Electr Eng 100:107930. https://doi.org/10.1016/j.compeleceng.2022.107930.1
Goswami R, Bhowmick B, Baishya S (2015) Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattices Microstruct 86:342–354. https://doi.org/10.1016/j.spmi.2015.07.064
Gu J, Keane J, Sapatnekar S, Kim CH (2008) Statistical leakage estimation of double gate FinFET devices considering the width quantization property. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(2):206–209. https://doi.org/10.1109/TVLSI.2007.909809
Guillorn M, Chang J, Bryant A, Fuller N, Dokumaci O, Wang X, Haensch W (2008) FinFET performance advantage at 22 nm: an AC perspective. In: 2008 Symposium on VLSI Technology. IEEE, pp 12–13. https://doi.org/10.1109/VLSIT.2008.4588544
Hayashi Y (1980) MOS field effect transistor. JP Patent Application S55-85706, June 24, 1980
Hisamoto D, Lee WC, Kedzierski J, Takeuchi H, Asano K, Kuo C, Hu C (2000) FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47(12):2320–2325. https://doi.org/10.1109/16.887014
Jaiswal S, Goswami R, Goswami M, Kandpal K (2023) Impact of interface trap distribution on the performance of LTPS TFT. SILICON. https://doi.org/10.1007/s12633-023-02503-6
Klaassen DBM, Slotboom JW, De Graaff HC (1992) Unified apparent bandgap narrowing in n-and p-type silicon. Solid-State Electron 35(2):125–129. https://doi.org/10.1016/0038-1101(92)90051-D
Kumar B, Chaujar R (2021) Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate all around (GS-GAA) FinFET. SILICON 13:919–927
Madan J, Chaujar R (2017) Influence of temperature variations on radio frequency performance of Pnin Gate all around tunnel-fet. In: 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, pp 1120–1124. https://doi.org/10.1109/rteict.2017.8256772
Pal RS, Sharma S, Dasgupta S (2017) Recent trend of FinFET devices and its challenges: a review. In: 2017 Conference on Emerging Devices and Smart Systems (ICEDSS). IEEE, pp 150–154. https://doi.org/10.1109/ICEDSS.2017.8073675
Pande P, Haasmann D, Han J, Moghadam HA, Tanner P, Dimitrijev S (2020) Electrical characterization of SiC MOS capacitors: a critical review. Microelectron Reliab 112:113790. https://doi.org/10.1016/j.microrel.2020.113790
Pandey R, Madan J, Sharma R, Dassi M, Chaujar R (2020) Built-in reliability investigation of gate-drain underlapped pnin-gaa-tfet for improved linearity and reduced intermodulation distortion. In: Energy systems, drives and automations: proceedings of ESDA 2019. Springer Singapore, pp 205–213. https://doi.org/10.1007/978-981-15-5089-8_19
Petrosyants KO, Silkin DS, Popov DA (2022) Comparative characterization of NWFET and FinFET transistor structures using TCAD modeling. Micromachines 13(8):1293
Sairam T, Zhao W, Cao Y (2007) Optimizing FinFET technology for high-speed and low-power design. In: Proceedings of the 17th ACM Great Lakes symposium on VLSI, pp 73–77. https://doi.org/10.1145/1228784.1228807
Sharma D, Vishvakarma SK (2015) Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron J 46(8):731–739. https://doi.org/10.1016/j.mejo.2015.05.008
Synopsys Inc. (2020). Sentaurus TCADVersion R-2020.09-SP1.
Thingujam T, Son DH, Kim JG, Cristoloveanu S, Lee JH (2020) Effects of interface traps and self-heating on the performance of GAA GaN vertical nanowire MOSFET. IEEE Trans Electron Devices 67(3):816–821. https://doi.org/10.1109/TED.2019.2963427
Toan HLM, Goswami R (2022) Impact of gate dielectric on overall electrical performance of Quadruple gate FinFET. Appl Phys A 128(2):103. https://doi.org/10.1007/s00339-021-052104
Van Langevelde R, Klaassen FM (1997) Effect of gate-field dependent mobility degradation on distortion analysis in MOSFETs. IEEE Trans Electron Devices 44(11):2044–2052. https://doi.org/10.1109/16.641382
Verma S, Tripathi SL (2022) Impact & analysis of inverted-T shaped Fin on the performance parameters of 14-nm heterojunction FinFET. SILICON 14(15):9441–9451. https://doi.org/10.1007/s12633-022-01708-5
Verma S, Narula V, Tripathi SL (2023) Performance analysis of multi-channel-multi-gate-based junctionless field effect transistor. IETE J Res. https://doi.org/10.1080/03772063.2023.2218318
Acknowledgements
This work is partly supported by DST FIST II, vide sanction no SR/FST/ET-II/2018/241.
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Das, P.S., Nath, D., Deb, D. et al. Mobility effects due to doping, temperature and interface traps in gate-all-around FinFETs. Microsyst Technol (2024). https://doi.org/10.1007/s00542-024-05637-8
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DOI: https://doi.org/10.1007/s00542-024-05637-8