Abstract
A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time.
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Foundation item: Supported by the National Key Pre-Research Project of China (413010701-3)
Biography: ZHANG Tao (1967–), male, Associate professor, research direction: signal processing and digital/analog mixed integrated circuits design.
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Zhang, T., Zou, X., Zhao, G. et al. A PLL clock frequency multiplier using dynamic current matching adaptive charge-pump and VCO frequency reuse. Wuhan Univ. J. of Nat. Sci. 12, 491–495 (2007). https://doi.org/10.1007/s11859-006-0072-7
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DOI: https://doi.org/10.1007/s11859-006-0072-7