Abstract
In this paper, low phase noise CMOS Phase Locked Loop (PLL) has been designed using a current source voltage-controlled oscillator (VCO), charge pump and Phase Frequency Detector (PFD). The proposed PLL VCO can operate in the band of 600 MHz to 5 GHz. The design has been simulated on cadence virtuoso tool at gpdk 90 nm technology scale with 2 V supply voltage. The phase noise of overall PLL is measured to be 125.53 dBc/Hz whereas the phase noise of VCO is 156.8 dBc/Hz. In addition, the PLL has a locking time of 6 µs due to the utilization of charge pump with dynamic Charge Transfer Switch (CTS).
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Bharti, M., Kumar, S., Rawat, A. (2024). Design of Low Phase Noise PLL with Improved Locking Time. In: Gabbouj, M., Pandey, S.S., Garg, H.K., Hazra, R. (eds) Emerging Electronics and Automation. E2A 2022. Lecture Notes in Electrical Engineering, vol 1088. Springer, Singapore. https://doi.org/10.1007/978-981-99-6855-8_36
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DOI: https://doi.org/10.1007/978-981-99-6855-8_36
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