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Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system

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Abstract

In this paper, a new model based on an improved Brent Kung (BK) parallel prefix network (PPN) algorithm is proposed and realized in the field programmable gate array (FPGA). This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying (DQPSK) precoder in 40 Gb/s polarization division multiplex (PolDM) DQPSK system. In the computation process, the computation complexity (area) optimization with fan-out limited is achieved. In the implementation, 770 FPGA slice registers are utilized, which save about 60% logic resources compared with the previous Kogge Stone (KS) algorithm.

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Authors and Affiliations

  1. Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, Ministry of Education, Beijing, 100876, China

    Zhou Li-ming  (周黎明), Zhang Yang-an  (张阳安), Ming-lun Zhang  (张明伦), Gai Wang  (王盖), Jin-nan Zhang  (张锦南), Yong-qing Huang  (黄永请) & Ling Li  (李玲)

Authors
  1. Zhou Li-ming  (周黎明)
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  2. Zhang Yang-an  (张阳安)
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  3. Ming-lun Zhang  (张明伦)
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  4. Gai Wang  (王盖)
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  5. Jin-nan Zhang  (张锦南)
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  6. Yong-qing Huang  (黄永请)
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  7. Ling Li  (李玲)
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Corresponding author

Correspondence to Zhou Li-ming  (周黎明).

Additional information

This work has been supported by the National High Technology Research and Development Program of China (No.2009AA01Z224), the National 111 Project (No.B07005), and the Program for Changjiang Scholars and Innovative Research Team in University of China (No.IRT0609).

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Li-ming, Z., Yang-an, Z., Zhang, Ml. et al. Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system. Optoelectron. Lett. 6, 446–448 (2010). https://doi.org/10.1007/s11801-010-0113-5

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  • DOI: https://doi.org/10.1007/s11801-010-0113-5

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