Abstract
A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET. Experimental results were used to validate this model. The extracted parameters from our model were t OX=20 nm, N D=1×1016 cm−3, t SSi=13.2 nm, consistent with the experimental values. The results show that the simulation results agree with experimental data well. It is found that the plateau can be strongly affected by doping concentration, strained-Si layer thickness and mass fraction of Ge in the SiGe layer. The model has been implemented in the software for strained silicon MOSFET parameter extraction, and has great value in the design of the strained-Si/SiGe devices.
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Foundation item: Projects(51308040203, 6139801) supported by National Ministries and Commissions, China; Projects(72105499, 72104089) supported by the Fundamental Research Funds for the Central Universities, China; Project(2010JQ8008) supported by the Natural Science Basic Research Plan in Shaanxi Province of China
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Wang, B., Zhang, Hm., Hu, Hy. et al. Physically based analytical model for plateau in gate C-V characteristics of strained silicon pMOSFET. J. Cent. South Univ. 20, 2366–2371 (2013). https://doi.org/10.1007/s11771-013-1745-y
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DOI: https://doi.org/10.1007/s11771-013-1745-y