Abstract
The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.
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Supported by the National Natural Science Foundation of China (No. 60776022, No. 60971061, No. 61076032), the Key Project of Natural Scence Foundation of Zhejiang Province, China (No. 21111219), the New Shoot Talents Program of Zhejing Province (No. 2008R40G2070015), the Student Scientific Research Innovation Project of Zhejiang Province.
Communication author: Wang Pengjun, born in 1966, male, Professor.
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Wang, P., Li, K. & Mei, F. Design of ternary adiabatic multiplier on switch-level. J. Electron.(China) 28, 375–382 (2011). https://doi.org/10.1007/s11767-011-0333-2
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DOI: https://doi.org/10.1007/s11767-011-0333-2