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Towards designing quantum reversible ternary multipliers

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Abstract

In recent years, extensive research has addressed multi-valued logic (MVL), especially ternary logic. Designing computational units based on multi-valued logic can reduce the number of operations as well as the chip occupied area. Furthermore, energy loss is one of the most important challenges in designing traditional electronic circuits. One of the most important approaches to overcome this problem is the design of circuits in reversible manner. A circuit is called reversible if and only if there is a one-to-one mapping between the input and output vectors. The combination of multi-valued logic and the concept of reversibility can create a unique design style with features such as high flexibility, low occupancy, and high speed. This paper proposed a new approach to design ternary reversible multipliers that can efficiently result in multiplying two ternary numbers. The multiplier’s circuits consist mainly of two parts, the calculation of the partial products and the sum of these partial products. After an in-depth study of the previously developed reversible ternary multipliers, we found that the most important challenge they faced was the large number of partial products produced because the multiplication of two one-digit ternary numbers produces a two-digit ternary number. In general, multiplying two one-digit ternary numbers can result in nine two-digit ternary numbers so that in eight of them, the most significant digit is zero, and in only one case, is nonzero. In this paper, we used this potential feature and proposed a method that ignores the most significant digit in the partial products. This technique can reduce the number of digits for summation by almost half. Then, a corrector circuit was designed that can detect and correct the results generated from ignoring the most significant digit in the partial products. Besides, for the partial product summation, this study proposed a new reversible ternary full-adder that is capable of performing the summation more efficiently. To evaluate the proposed approach, two reversible ternary multipliers were designed and implemented. The results of comparisons show that the proposed 2-digit and 3-digit reversible ternary multipliers are better than other designs so that they give about 3% and 11% improvements in terms of quantum cost, respectively, compared to the previous best related ones.

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Authors and Affiliations

  1. Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran

    Mohammad-Ali Asadi & Mohammad Mosleh

  2. Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

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  1. Mohammad-Ali Asadi
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  2. Mohammad Mosleh
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  3. Majid Haghparast
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Correspondence to Mohammad Mosleh.

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Asadi, MA., Mosleh, M. & Haghparast, M. Towards designing quantum reversible ternary multipliers. Quantum Inf Process 20, 226 (2021). https://doi.org/10.1007/s11128-021-03161-6

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