Dual P⁺-Wire Double-Gate Junctionless MOSFET with 10-nm Regime for Low Power Applications

Abstract

The present study simulated and investigated a 3D double-gate junctionless transistor with a gate length of 10 nm and using dual P⁺-wire (DPW) on the leftmost and rightmost ends of the main channel in the DC and AC modes. The DC analysis showed that more carriers are depleted from the middle of the channel in the DPW structure compared to the same structure without DPW which is the main structure of this study. Moreover, the drain leakage currents at temperatures of 233 K, 300 K, 400 K, and 500 K experienced significant reductions in the DPW structure compared to the main structure. The results are also indicative of the improved drain-induced barrier lowering (DIBL) and I_ON/I_OFF in the DPW structure compared to the main structure. On the other hand, the AC analysis showed that the parasitic capacitances in the DPW structure are reduced at a frequency of 1 MHz compared to the main structure, in turn increasing the cut-off frequency. The analysis results also showed that maximum available power gain (GMA), maximum stable power gain (GMS), max transducer power gain, and unilateral power were improved in the DPW structure compared to the main structure.