Scalability of GaN Nanowire FET beyond 5 nm: A Simulation Study

Abstract

In this work, design optimization and performance analysis of GaN nanowire (NW) field effect transistors (FETs) for gate length (L_g) of 3 nm, 5 nm, and 7 nm is performed to evaluate their performance in electronics and biosensing applications. The simulation and modeling are carried out using self-consistent Poisson and Schrodinger equations based on a non-equilibrium Green function (NEGF) approach using Silvaco ATLAS. The simulation results reveal the following: (1) ~ 40.13% increase in the integration density and ~ 33.59% increase in the power density, (2) ~ 25.35% increase in I_on/I_off ratio for nanowire channel thickness (T_nw) of 1.6 nm and ~ 38.78% increase in I_on/I_off ratio for T_nw = 80 nm, (3) a way to change the mode of operation from E-mode to D-mode and vice-versa based on T_nw variations, and (4) switching speed gain of 0.78% for NW FETs with T_nw = 1.6 nm and 0.09% for NW FETs with T_nw = 80 nm for gate length scaling of 7 nm to 5 nm and a loss of ~ 0.46% and ~ 0.09% for 7 nm to 3 nm. The device has been designed and optimized for digital applications with an I_on/I_off ratio of ~ 10⁸ and sensitivity of ~ 21.8 mS for a biosensing application.