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Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments

  • International Electron Devices and Materials Symposium 2019
  • Published:
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Abstract

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

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Acknowledgments

The authors cordially thank United Microelectronics Corporation in Taiwan for providing valuable 12'' wafers.

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Authors and Affiliations

  1. Department of Electronic Engineering, Minghsin University of Science and Technology, No. 1, Xinxing Rd., Xinfeng, Hsinchu, 30401, Taiwan

    Ching-Chuan Chou, Tien-Szu Shen, Jian-Ming Chen, Cheng-Hsun-Tony Chang & Mu-Chun Wang

  2. Department of Materials and Resources Engineering, National Taipei University of Technology, Taipei, 10608, Taiwan

    Shea-Jue Wang

  3. Department of Electrical Engineering, National University of Kaohsiung, 700, Kaohsiung University Rd., Nanzih District, Kaohsiung, 81148, Taiwan

    Wen-How Lan

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  1. Ching-Chuan Chou
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  2. Tien-Szu Shen
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Correspondence to Wen-How Lan or Mu-Chun Wang.

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Chou, CC., Shen, TS., Chen, JM. et al. Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments. J. Electron. Mater. 49, 6764–6775 (2020). https://doi.org/10.1007/s11664-020-08182-y

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  • DOI: https://doi.org/10.1007/s11664-020-08182-y

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