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On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric

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Abstract

In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous one-dimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-κ gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO2 as a gate dielectric. A study of a ZnO/ZrO2 interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO2 gate dielectric exhibits a low subthreshold slope (131 mV decade−1), low gate leakage current density (2.94 × 10−7 A cm−2) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of −1.4 V, which is attributed to the existence of oxygen vacancies.

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Acknowledgments

The authors would like to acknowledge the Central Electronics Engineering Research Institute (CSIR-CEERI) Pilani, India, and Material Research Center MNIT Jaipur, India, for providing the experimental facilities for this work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Indian Institute of Information Technology Allahabad, Prayagraj, 211015, India

    Kavindra Kandpal

  2. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, Pilani Campus, Pilani, 333031, India

    Navneet Gupta & Chandra Shekhar

  3. Smart Sensors Area, CSIR-Central Electronics Engineering Research Institute Pilani, Pilani, 333031, India

    Jitendra Singh

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  1. Kavindra Kandpal
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  2. Navneet Gupta
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Correspondence to Kavindra Kandpal.

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Kandpal, K., Gupta, N., Singh, J. et al. On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric. J. Electron. Mater. 49, 3156–3164 (2020). https://doi.org/10.1007/s11664-020-08055-4

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  • DOI: https://doi.org/10.1007/s11664-020-08055-4

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