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Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits

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Abstract

Single-event transient pulse quenching (Quenching effect) is employed to effectively mitigate W SET (SET pulse width). It enhanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, parameter variation is another serious issue that significantly affects circuit’s performance and single-event response. Monte Carlo simulations combined with TCAD (Technology Computer-Aided Design) simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider W SET spread range. The difference of W SET range between no quenching and quenching is smaller in NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) simulation than that in PMOS’ (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor), so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness (TOXE) and channel length variation (XL) mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average W SET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.

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Authors and Affiliations

  1. Micro-electric Centre, Harbin Institute of Technology, Harbin, 150001, China

    TianQi Wang, LiYi Xiao, Bin Zhou & ChunHua Qi

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  1. TianQi Wang
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  2. LiYi Xiao
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  3. Bin Zhou
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Correspondence to LiYi Xiao.

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Wang, T., Xiao, L., Zhou, B. et al. Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits. Sci. China Technol. Sci. 57, 322–331 (2014). https://doi.org/10.1007/s11431-013-5441-9

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  • DOI: https://doi.org/10.1007/s11431-013-5441-9

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