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Mirror image: newfangled cell-level layout technique for single-event transient mitigation

  • Article
  • Nuclear Science & Technology
  • Published:
Chinese Science Bulletin

Abstract

Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cell-circuit module to mitigate single event transient (SET) sensitivity. The mirror image (MI) technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twin-well bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25 %, and can mitigate the SET pulse width from the posterior-stage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61376109).

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Authors and Affiliations

  1. Micro-electronics and Microprocessor Institute, National University of Defense Technology, Changsha, 410073, China

    Pengcheng Huang, Zhengfa Liang, Jianjun Chen, Chunmei Hu & Yibai He

  2. National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, 410073, China

    Shuming Chen

Authors
  1. Pengcheng Huang
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  2. Shuming Chen
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  3. Zhengfa Liang
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  4. Jianjun Chen
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  5. Chunmei Hu
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  6. Yibai He
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Corresponding author

Correspondence to Shuming Chen.

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Huang, P., Chen, S., Liang, Z. et al. Mirror image: newfangled cell-level layout technique for single-event transient mitigation. Chin. Sci. Bull. 59, 2850–2858 (2014). https://doi.org/10.1007/s11434-014-0409-0

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  • DOI: https://doi.org/10.1007/s11434-014-0409-0

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