Abstract
A new low leakage 3×VDD-tolerant electrostatic discharge (ESD) detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process. Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current. No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well. The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier (STSCR) under the ESD stress. Under normal operating conditions, all the devices are free from over-stress voltage threat. The leakage current is 88 nA under 3×VDD bias at 25°C. The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.
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Yang, Z., Liu, H. & Wang, S. Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process. Sci. China Technol. Sci. 56, 2046–2051 (2013). https://doi.org/10.1007/s11431-013-5278-2
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DOI: https://doi.org/10.1007/s11431-013-5278-2