Abstract
Hardware security remains as a major concern in the circuit design ow. Logic block based encryption has been widely adopted as a simple but effective protection method. In this paper, the potential threat arising from the rapidly developing field, i.e., machine learning, is researched. To illustrate the challenge, this work presents a standard attack paradigm, in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic encryption. Backed with validation results obtained from both combinational and sequential benchmarks, the presented attack scheme can specifically accelerate the decryption process of partial keys, which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.
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References
Bhunia S, Tehranipoor M. Introduction to hardware security. In Hardware Security: A Hands-on Learning Approach (1st edition), Bhunia S, Tehranipoor M (eds.), Morgan Kaufmann, 2019, pp.1-20. https://doi.org/10.1016/B978-0-12-812477-2.00006-X.
Rajendran J, Sinanoglu O, Karri R. Regaining trust in VLSI design: Design-for-trust techniques. Proceedings of the IEEE, 2014, 102(8): 1266-1282. https://doi.org/10.1109/JPROC.2014.2332154.
Hospodar G, Gierlichs B, Mulder E D, Verbauwhede I, Vandewalle J. Machine learning in side-channel analysis: A first study. Journal of Cryptographic Engineering, 2011, 1(4): Article No. 293. https://doi.org/10.1007/s13389-011-0023-x.
Gilmore R, Hanley N, O'Neill M. Neural network based attack on a masked implementation of AES. In Proc. the 2015 IEEE International Symposium on Hardware Oriented Security and Trust, May 2015, pp.106-111. https://doi.org/10.1109/HST.2015.7140247.
Maghrebi H, Portigliatti T, Prouff E. Breaking cryptographic implementations using deep learning techniques. In Proc. the 2016 International Conference on Security, Privacy, and Applied Cryptography Engineering, December 2016, pp.3-26. https://doi.org/10.1007/978-3-319-49445-6_1.
Das D, Golder A, Danial J, Ghosh S, Raychowdhury A, Sen S. X-DeepSCA: Cross-device deep learning side channel attack. In Proc. the 56th ACM/IEEE Design Automation Conference, June 2019, Article No. 134. https://doi.org/10.1145/3316781.3317934.
Das D, Danial J, Golder A, Ghosh S, Wdhury A R, Sen S. Deep learning side-channel attack resilient AES-256 using current domain signature attenuation in 65nm CMOS. In Proc. the 2020 IEEE Custom Integrated Circuits Conference, March 2020. https://doi.org/10.1109/CICC48029.2020.9075889.
Shan W W, Zhang S, Xu J M, Lu M Y, Shi L X, Yang J. Machine learning assisted side-channel-attack counter-measure and its application on a 28-nm AES circuit. IEEE Journal of Solid-State Circuits, 2020, 55(3): 794-804. https://doi.org/10.1109/JSSC.2019.2953855.
Roy J A, Koushanfar F, Markov I L. EPIC: Ending piracy of integrated circuits. In Proc. the 2008 Design, Automation and Test in Europe, March 2008, pp.1069-1074. https://doi.org/10.1109/DATE.2008.4484823.
Rajendran J, Zhang H, Zhang C, Rose G S, Pino Y, Sinanoglu O, Karri R. Fault analysis-based logic encryption. IEEE Transactions on Computers, 2015, 64(2): 410-424. https://doi.org/10.1109/TC.2013.193.
Pritika K, Vinodhini M. Logic encryption of combinational circuits. In Proc. the 3rd International Conference on Electronics, Materials Engineering & Nano-Technology, August 2019. https://doi.org/10.1109/IEMENTech48150.2019.8981198.
Kiryakina M A, Kuzmicheva S A, Ivanov M A. Encrypted PRNG by logic encryption. In Proc. the 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, January 2020, pp.356-358. https://doi.org/10.1109/EIConRus49466.2020.9038921.
Karmakar R, Chatopadhyay S, Kapur R. Encrypt flip-flop: A novel logic encryption technique for sequential circuits. arXiv:1801.04961, 2018. https://arxiv.org/abs/1801.04961, January 2021.
Šišejković D, Merchant F, Leupers R, Ascheid G, Kegreiss S. Inter-Lock: Logic encryption for processor cores beyond module boundaries. In Proc. the 2019 IEEE European Test Symposium, May 2019. https://doi.org/10.1109/ETS.2019.8791528.
Karmakar R, Prasad N, Chattopadhyay S, Kapur R, Sengupta I. A new logic encryption strategy ensuring key interdependency. In Proc. the 30th International Conference on VLSI Design and the 16th International Conference on Embedded Systems, January 2017, pp.429-434. https://doi.org/10.1109/VLSID.2017.29.
Juretus K, Savidis I. Reduced overhead gate level logic encryption. In Proc. the 2016 International Great Lakes Symposium on VLSI, May 2016, pp.15-20. https://doi.org/10.1145/2902961.2902972.
Chen X M, Liu Q Y, Wang Y, Xu Q, Yang H Z. Low-overhead implementation of logic encryption using gate replacement techniques. In Proc. the 18th International Symposium on Quality Electronic Design, March 2017, pp.257-263. https://doi.org/10.1109/ISQED.2017.7918325.
Yasin M, Mazumdar B, Ali S S, Sinanoglu O. Security analysis of logic encryption against the most effective side-channel attack: DPA. In Proc. the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 2015, pp.97-102. https://doi.org/10.1109/DFT.2015.7315143.
Yasin M, Rajendran J, Sinanoglu O, Karri R. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(9): 1411-1424. https://doi.org/10.1109/TCAD.2015.2511144.
Lee Y W, Touba N A. Improving logic obfuscation via logic cone analysis. In Proc. the 16th Latin-American Test Symposium, March 2015. https://doi.org/10.1109/LATW.2015.7102410.
Plaza S M, Markov I L. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(6): 961-971. https://doi.org/10.1109/TCAD.2015.2404876.
Subramanyan P, Ray S, Malik S. Evaluating the security of logic encryption algorithms. In Proc. the 2015 IEEE International Symposium on Hardware Oriented Security and Trust, May 2015, pp.137-143. https://doi.org/10.1109/HST.2015.7140252.
Yasin M, Mazumdar B, Rajendran J, Sinanoglu O. SAR-Lock: SAT attack resistant logic locking. In Proc. the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, May 2016, pp.236-241. https://doi.org/10.1109/HST.2016.7495588.
Xie Y, Srivastava A. Anti-SAT: Mitigating SAT attack on logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38(2): 199-207. https://doi.org/10.1109/TCAD.2018.2801220.
Chen Y C. Tree-based logic encryption for resisting SAT attack. In Proc. the 26th IEEE Asian Test Symposium, November 2017, pp.46-51. https://doi.org/10.1109/ATS.2017.21.
Shen Y Q, Rezaei A, Zhou H. SAT-based bit-flipping attack on logic encryptions. In Proc. the 2018 Design, Automation & Test in Europe Conference & Exhibition, March 2018, pp.629-632. https://doi.org/10.23919/DATE.2018.8342086.
Shen Y Q, Li Y, Kong S Y, Rezaei A, Zhou H. SigAttack: New high-level SAT-based attack on logic encryptions. In Proc. the 2019 Design, Automation & Test in Europe Conference & Exhibition, March 2019, pp.940-943. https://doi.org/10.23919/DATE.2019.8714924.
Kasarabada Y, Chen S Y, Vemuri R. On SAT-based attacks on encrypted sequential logic circuits. In Proc. the 20th International Symposium on Quality Electronic Design, March 2019, pp.204-211. https://doi.org/10.1109/ISQED.2019.8697421.
Rajendran J, Pino Y, Sinanoglu O, Karri R. Logic encryption: A fault analysis perspective. In Proc. the 2012 Design, Automation & Test in Europe Conference & Exhibition, March 2012, pp.953-958. https://doi.org/10.1109/DATE.2012.6176634.
Karmakar R, Chattopadhyay S, Kapur R. Enhancing security of logic encryption using embedded key generation unit. In Proc. the 2017 International Test Conference in Asia (ITC-Asia), September 2017, pp.131-136. https://doi.org/10.1109/ITC-ASIA.2017.8097127.
Mobaraki S, Amirkhani A, Atani R E. A novel PUF based logic encryption technique to prevent SAT attacks and trojan insertion. In Proc. the 9th International Symposium on Telecommunications, December 2018, pp.507-513. https://doi.org/10.1109/ISTEL.2018.8661086.
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Zhong, Y., Feng, JH., Cui, XX. et al. Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. J. Comput. Sci. Technol. 36, 1102–1117 (2021). https://doi.org/10.1007/s11390-021-0846-6
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DOI: https://doi.org/10.1007/s11390-021-0846-6