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New Electronically Tunable Four-Quadrant Analog Multiplier Employing Single EXCCCII and Its Applications

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Abstract

In this manuscript, a new four-quadrant analog multiplier has been designed using a current-mode analog building block namely an extra-X second-generation current-controlled conveyor, and two MOS transistors. The passive components have not been used in the design of the proposed analog multiplier which leads to a simpler configuration. The proposed multiplier has been simulated using the PSPICE simulation tool with 0.18 µm Taiwan semiconductor manufacturing company parameters. The obtained simulation results are in close agreement with the theory. The performance of the proposed multiplier is satisfactory for the input voltage range of ± 0.6 V and a supply voltage of ± 0.9 V. The power consumption of the proposed multiplier is 0.26 mW. The multiplier is less sensitive to variations in temperature. The − 3 dB bandwidth of the proposed multiplier is 287.44 MHz whereas the output noise is 6.02 nV/√Hz for a 1 kΩ load. The non-ideal analysis of the proposed multiplier has also been done including all parasitic impedances. The performance of the proposed multiplier is found to be satisfactory in the application of amplitude modulation, squarer, and frequency doubler circuits.

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Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

References

  1. Gilbert, B. (1968). A precise four-quadrant multiplier with sub nano second response. IEEE Journal of Solid-State Circuits, 3(4), 365–373. https://doi.org/10.1109/JSSC.1968.1049925

    Article  Google Scholar 

  2. Babanezhad, J. N., & Temes, G. C. (1985). A 20–v four-quadrant CMOS analog multiplier. IEEE Journal of Solid-State Circuits, 20(6), 1158–1168. https://doi.org/10.1109/JSSC.1985.1052454

    Article  Google Scholar 

  3. Qin, S. C., & Geiger, R. L. (1987). A ± 5–v CMOS analog multiplier. IEEE Journal of Solid-State Circuits, 22(6), 1143–1146. https://doi.org/10.1109/JSSC.1987.1052866

    Article  Google Scholar 

  4. Yasumoto, M., & Enomoto, T. (1987). Integrated MOS four-quadrant analogue multiplier using switched-capacitor technique. Electronics Letters, 18(18), 769. https://doi.org/10.1049/el:19820520

    Article  Google Scholar 

  5. Peña-Finol, J. S., & Connelly, J. A. (1987). A MOS four-quadrant analog multiplier using the quarter-square technique. IEEE Journal of Solid-State Circuits, 22(6), 1064–1073. https://doi.org/10.1109/JSSC.1987.1052856

    Article  Google Scholar 

  6. Khachab, N. I., & Ismail, M. (1989). MOS multiplier/divider cell for analogue VLSI. Electronics Letters, 25(23), 1550–1552. https://doi.org/10.1049/el:19891042

    Article  Google Scholar 

  7. Khachab, N. I., & Ismail, M. (1991). A nonlinear CMOS analog cell for VLSI signal and information processing. IEEE Journal of Solid-State Circuits, 26(11), 1689–1699. https://doi.org/10.1109/4.98991

    Article  Google Scholar 

  8. Liu, S. I., Wu, D. S., Tsao, H. W., Wu, J., & Tsay, J. H. (1993). Nonlinear circuit applications with current conveyors. IEE Proceedings, Part G: Circuits, Devices and Systems, 140(1), 1–6. https://doi.org/10.1049/ip-g-2.1993.0001

    Article  Google Scholar 

  9. Ismail, M., Brannen, R., Takagi, S., Fujii, N., Khachab, N. I., Khan, R., & Aaserud, O. (1994). Configurable CMOS multiplier/divider circuits for analog VLSI. Analog Integrated Circuits and Signal Processing, 5(3), 219–234. https://doi.org/10.1007/BF01261414

    Article  Google Scholar 

  10. Elwan, H., & Soliman, A. (1996). CMOS differential current conveyors and applications for analog VLSI. Analog Integrated Circuits and Signal Processing, 11(1), 35–45. https://doi.org/10.1007/BF00174237

    Article  Google Scholar 

  11. Chiu, W., Liu, S.-I., Tsao, H.-W., & Chen, J.-J. (1996). CMOS differential difference current conveyors and their applications. IEE Proceedings - Circuits, Devices and Systems, 143(2), 91. https://doi.org/10.1049/ip-cds:19960223

    Article  MATH  Google Scholar 

  12. Premont, C., Abouchi, N., Grisel, R., & Chante, J. P. (1999). A BiCMOS current conveyor based four-quadrant analog multiplier. Analog Integrated Circuits and Signal Processing, 19(2), 159–162. https://doi.org/10.1023/A:1008305916139

    Article  Google Scholar 

  13. El-Adawy, A. A., Soliman, A. M., & Elwan, H. O. (2000). A novel fully differential current conveyor and applications for analog VLSI. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(4), 306–313. https://doi.org/10.1109/82.839666

    Article  Google Scholar 

  14. Surakampontorn, W., Khanittha, K., Chalermpan, F. (2002). A simple current mode multiplier divider circuit using OTAs. In International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2002) (pp. 658–661).

  15. Kaewdang, K., Fongsamut, C., & Surakampontorn, W. (2003). A wide-band current-mode OTA-based analog multiplier-divider. Proceedings - IEEE International Symposium on Circuits and Systems, 1, 349–352. https://doi.org/10.1109/iscas.2003.1205572

    Article  Google Scholar 

  16. Keskin, A. Ü. (2004). A four quadrant analog multiplier employing single CDBA. Analog Integrated Circuits and Signal Processing, 40(1), 99–101. https://doi.org/10.1023/B:ALOG.0000031440.22112.eb

    Article  Google Scholar 

  17. Ciftcioglu, S., Kuntman, H., & Zeki. (2005). New high-performance CMOS differential current conveyor realization. In Proceedings of ELECO 2005: The 4th International Conference on Electrical and Electronics, December 2005 (pp. 68–71).

  18. Riewruja, V., & Rerkratn, A. (2005). Analog multiplier using operational amplifiers. In International Conference on Control, Automation, and Systems (ICCAS2005), March 2005, 1–4.

  19. Zeki, A. (2005). DXCCII-based four-quadrant analog multipliers using triode MOSFETs. 2 (June 2014), 1–6.

  20. Siripruchyanun, M. (2007). A design of analog multiplier and divider using current controlled current differencing buffered amplifiers. 2007 International Symposium on Integrated Circuits ISIC, 1, 568–571. https://doi.org/10.1109/ISICIR.2007.4441925

    Article  Google Scholar 

  21. Jaikla, W., & Siripruchyanun, M. (2007). A novel current-mode multiplier/divider employing only single Dual-Output Current Controlled CDTA. 2007 International Symposium on Communications and Information Technologies, 30(2), 106–109. https://doi.org/10.1109/ISCIT.2007.4391994.

  22. Jaikla, W., & Siripruchyanun, M. (2007). A current-mode multiplier/divider employing only single Dual-Output Current Controlled CDTA. 2007 International Symposium on Communications and Information Technologies, 30(2), 106–109. https://doi.org/10.1109/ISCIT.2007.4391994.

  23. Siripruchyanun, M., & Jaikla, W. (2008). A current-mode analog multiplier/divider based on CCCDTA. AEU - International Journal of Electronics and Communications, 62(3), 223–227. https://doi.org/10.1016/j.aeue.2007.03.009

    Article  Google Scholar 

  24. Narksarp, W., Pawarangkoon, P., Kiranon, W., & Wadkien, P. (2009). A four-quadrant current-mode multiplier/divider building block. 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009, 1, 574–577. https://doi.org/10.1109/ECTICON.2009.5137072.

  25. Young, T. C. (2009). Improving the U.S. Military’S Adaptability Against the Salafist-Jihadi Threat. June 2009, 41–48. https://doi.org/10.1049/iet-cds.

  26. Pisutthipong, N., & Siripruchyanun, M. (2009). A novel simple current-mode multiplier/divider employing only single multiple-output current controlled CTTA. IEEE Region 10 Annual International Conference, Proceedings/TENCON, 1–4. https://doi.org/10.1109/TENCON.2009.5395877.

  27. Riewruja, V., & Rerkratn, A. (2010). Analog multiplier using operational amplifiers. Indian Journal of Pure and Applied Physics, 48(1), 67–70.

    Google Scholar 

  28. Petchakit, W., Kiranon, W., Wardkien, P., & Petchakit, S. (2010). A current-mode CCCII-based analog multiplier/divider. ECTI-CON 2010 - The 2010 ECTI International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (pp. 221–224).

  29. Riewruja, V., & Rerkratn, A. (2011). Four-quadrant analogue multiplier using operational amplifier. International Journal of Electronics, 98(4), 459–474. https://doi.org/10.1080/00207217.2010.520155

    Article  Google Scholar 

  30. Myderrizi, I., Minaei, S., & Yuce, E. (2011). CCII+based fully CMOS four-quadrant multiplier. Canadian Conference on Electrical and Computer Engineering, 000759–000762. https://doi.org/10.1109/CCECE.2011.6030557.

  31. Tangsrirat, W., Pukkalanun, T., Mongkolwai, P., & Surakampontorn, W. (2011). Simple current-mode analog multiplier, divider, square-rooter and squarer based on CDTAs. AEU - International Journal of Electronics and Communications, 65(3), 198–203. https://doi.org/10.1016/j.aeue.2010.02.017

    Article  Google Scholar 

  32. Mongkolwai, P., & Tangsrirat, W. (2011). CFTA-based current multiplier/divider circuit. International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS), 2011, 1–4. https://doi.org/10.1109/ISPACS.2011.6146074

    Article  Google Scholar 

  33. Pandey, R., Pandey, N., Sriram, B., & Paul, S. K. (2012). Single OTRA based analog multiplier and its applications. ISRN Electronics, 2012(Mdcc), 1–7. https://doi.org/10.5402/2012/890615.

  34. Kumngern, M. (2013). A DXCCII-based four-quadrant multiplier. Proceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference, PEOCO 2013, June, 738–741. https://doi.org/10.1109/PEOCO.2013.6564644.

  35. Kumngern, M., & Torteanchai, U. (2013). A CMOS current-mode multiplier/divider using a current amplifier. Proceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference, PEOCO 2013, June, 742–745. https://doi.org/10.1109/PEOCO.2013.6564645.

  36. Abuelma’atti, M. T., & Al-Qahtani, M. A. (2014). A current-mode current-controlled current-conveyor-based analogue multiplier/divider. International Journal of Electronics, 85(1), 71–77. https://doi.org/10.1080/002072198134364

    Article  Google Scholar 

  37. Pathak, K., Singh, J. K. A., Senani, R., & R. (2014). New Multiplier/Divider Using a Single CDBA. American Journal of Electrical and Electronic Engineering, 2(3), 98–102. https://doi.org/10.12691/ajeee-2-3-7

    Article  Google Scholar 

  38. Arora, T. S., & Sharma, R. K. (2016). A novel cubic generator realised by CCIII-based four quadrant analog multiplier and divider. Indian Journal of Science and Technology, 9(38), 1. https://doi.org/10.17485/ijst/2016/v9i38/100026

    Article  Google Scholar 

  39. Bhanja, M., & Ray, B. N. (2016). OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(2), 638–649. https://doi.org/10.1109/TVLSI.2015.2406953.

  40. Lawanwisut, S., Satthaphol, P., Payakkakul, K., Pipatthitikorn, P., & Siripruchyanun, M. (2016). A Temperature-insensitive Current-mode Multiplier/Divider Using only Double-output VDTA. Procedia Computer Science, 86(March), 156–159. https://doi.org/10.1016/j.procs.2016.05.042

    Article  Google Scholar 

  41. Chadha, U., & Arora, T. S. (2017). Four quadrant analog multiplier/divider employing single OTRA. Communication and Computing Systems - Proceedings of the International Conference on Communication and Computing Systems, ICCCS, 2016(2011), 635–639. https://doi.org/10.1201/9781315364094-115

    Article  Google Scholar 

  42. Tuntrakool, S., Suwanjan, P., & Jaikla, W. (2017). Temperature insensitive current-mode four quadrant multiplier using single CFCTA. MATEC Web of Conferences, 95, 4–7. https://doi.org/10.1051/matecconf/20179514001

    Article  Google Scholar 

  43. Roy, S., Paul, T. K., & Pal, R. R. (2017). A new method of realization of four-quadrant analog multiplier using operational amplifiers and MOSFETs. Journal of Physical Sciences, 22(2017), 163–173.

    Google Scholar 

  44. Ettaghzouti, T., Hassen, N., Garradhi, K., & Besbes, K. (2018). Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit. Turkish Journal of Electrical Engineering and Computer Sciences, 26(2), 882–894. https://doi.org/10.3906/elk-1708-179

    Article  Google Scholar 

  45. Roy, S., Paul, T. K., Maiti, S., & Pal, R. R. (2018). Two new analog multipliers/dividers employing single current differencing buffer amplifier. AEU - International Journal of Electronics and Communications, 88(March), 11–19. https://doi.org/10.1016/j.aeue.2018.03.002

    Article  Google Scholar 

  46. Rajpoot, J., & Maheshwari, S. (2020). High performance four-quadrant analog multiplier using DXCCII. Circuits, Systems, and Signal Processing, 39(1), 54–64. https://doi.org/10.1007/s00034-019-01179-x

    Article  Google Scholar 

  47. Roy, S., & Pal, R. R. (2020). Single fully differential second generation current conveyor based four-quadrant analog multiplier design and its applications. Chinese Journal of Electronics, 29(5), 841–851. https://doi.org/10.1049/cje.2020.08.012

    Article  Google Scholar 

  48. Kumar, A. (2021). Single EXCCII-based analog multiplier structure. Journal of Circuits, Systems and Computers, 30(6), 1. https://doi.org/10.1142/S0218126621501073

    Article  Google Scholar 

  49. Raj, A., Bhaskar, D. R., & Kumar, P. (2021). Novel architecture of four quadrant analog multiplier/divider circuit employing single CFOA. Analog Integrated Circuits and Signal Processing, 108(3), 689–701. https://doi.org/10.1007/s10470-021-01915-x

    Article  Google Scholar 

  50. Sharma, V. K., Parveen, T., & Ansari, M. S. (2021). Four quadrant analog multiplier based memristor emulator using single active element. AEU - International Journal of Electronics and Communications, 130, 153575. https://doi.org/10.1016/j.aeue.2020.153575

    Article  Google Scholar 

  51. Dhawan, R., Aggarwal, B., Narang, N., & Rai, S. K. (2022). A new low voltage current mode analog multiplier/divider circuit based on FGMOS translinear loop. Iranian Journal of Science and Technology - Transactions of Electrical Engineering, 46(2), 381–394. https://doi.org/10.1007/s40998-021-00476-z

    Article  Google Scholar 

  52. Maheshwari, S. (2013). Current Conveyor all-pass sections: Brief review and novel solution. The Scientific World Journal, 2013, 1–6. https://doi.org/10.1155/2013/429391

    Article  Google Scholar 

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Das, R., Rai, S.K. New Electronically Tunable Four-Quadrant Analog Multiplier Employing Single EXCCCII and Its Applications. Wireless Pers Commun 131, 165–186 (2023). https://doi.org/10.1007/s11277-023-10422-3

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