Skip to main content
SpringerLink
Log in

High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

In this paper, a soft error hardened circuit with the aim ofavoiding and detecting-correctingthe soft error strikesat the same timing phase is proposed for high-speed memory applications. The proposed design is completely immune to multiple soft errors occurring in any of the nodes. The avoidance part and detection-correction part are the two major parts that tolerate multiple particle strikes. The proposed design can detect and correct a single particle strike at single node and at multiple nodes.A set of simulations are made in CMOS technology to validate the proposed circuit in terms of delay, power, and area overheads which are the main requirements of VLSI design. Compared with other techniques it is shown that the proposed circuit achieves 1.124 μm power consumption, and142.68ps delay overheads. The work also investigates about Monte Carlo simulations along with the impact of process, voltage and temperature (PVT) variations and shows that the proposed circuit is highly reliable and less sensitive to soft errors compared with other existing soft error latches.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

Data Availability

Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.

References

  1. Argyrides, C. A., Reviriego, P., Pradan, D. K., & Maestro, A. K. (2010). Matrix-based codes for adjacent error correction. IEEE Transactions on Nuclear Science, 57(4), 2106–2111

    Article  Google Scholar 

  2. Neuberger, G., De Lima Kastensmidt, F. G., & Reis, R. (2005). An automatic technique for optimizing reed-solomon codes to improve fault tolerance in memories. IEEE Design & Test of Computers, 22(1), 50–58

    Article  Google Scholar 

  3. Ming, Z., Yi, X. L., Chang, L., & Wei, Z. J. (2011). Reliability of memories protected by multibit error correction codes against MBUs. IEEE Transactions on Nuclear Science, 58(1), 289–295

    Article  Google Scholar 

  4. Xuan, S. X., Li, N., & Tong, J. (2013). SEU hardened flip-flop based on dynamic logic. IEEE Transactions on Nuclear Science, 60(5), 3932–3936

    Article  Google Scholar 

  5. Montesinos, P., Liu, W., & Torrellas, J. (2007). Using register lifetime predictions to protect register files against soft errors. In Proceedings of37th Annual IEEE/FIP International Conference on Dependable Systems and Networks (DSN’07) (pp. 286-296). Edinburgh, UK

  6. Omana, M., Rossi, D., & Metra, C. (2010). High performance robust latches. IEEE Transactions on Computers, 59(11), 1455–1465

    Article  MATH  Google Scholar 

  7. Nan, H., & Choi, K. (2012). High performance low cost and robust soft error tolerant latch designs for nanoscale CMOS technology. IEEE Transactions on Circuits & Systems, 59(7), 1445–1457

    Article  Google Scholar 

  8. Trang Dang, L. D., Kim, J. S., & Chang, I. J. (2017). We-Quatro: Radiation Hardened SRAM cell with parametric process variation tolerance. IEEE Transactions on Nuclear Science, 60(5), 2489–2496

    Article  Google Scholar 

  9. Das, S., Tokunaga, C., Pant, S., Ma, W. H., Kalaiselvan, S., Lai, K., Bull, D. M. & Blaauw, D. T. (2009). RazorII: in situ error detection and correction for PVT and SER tolerance. IEEE Journal of Solid-State Circuits, 44(1), 32–48

  10. Lin, Y., Zwolinski, M., & Halak, B. (2016). A low-cost, radiation-hardened method for pipeline protection in microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(5), 1688–1701

    Article  Google Scholar 

  11. Zhang, M., Mitra, S., Mark, T. M., Seifert, N., Wang, N. J., Shi, Q., Kim, K. S., Shanbhag, N. R., & Patel, S. J. (2006). Sequential element design with built-in soft error resilience. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12), 1368–1378

    Article  Google Scholar 

  12. Shirinzadeh, S., & Asli, R. N. (2012). A Novel soft error hardened latch design in90nm CMOS. In Proceedings of 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012) (pp. 60-63). Shiraz, Iran

  13. Lin, S., Kim, Y. B., & Lombardi, F. (2011). Design and performance evaluation of radiation hardened latches for nanoscalecmos. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(7), 1315–1319

    Article  Google Scholar 

  14. She, X., Li, N., & Tong, J. (2012). SEU tolerant latch based on error detection. IEEE Transactions on Nuclear Science, 59(1), 211–214

    Article  Google Scholar 

  15. Fazeli, M., Miremadi, S. G., Ejlali, A., & Patooghy, A. (2009). Low energy single event upset/single event transient tolerant latch for deep submicron technologies. IET Computers & Digital Techniques, 3(3), 289–303

    Article  Google Scholar 

  16. Rajaei, R., Tabandeh, M., & Fazeli, M. (2014). Single event multiple upset (semu) tolerant latch designs in presence of process and temperature variations. Journal of Circuits Systems and Computers, 24(1), 1–30

    Google Scholar 

  17. Li, H. C., Xiao, L. Y., Li, J., & Qi, C. H. (2019). High robust and cost effective double node upset tolerant latch design for nanoscalecmos technology. Microelectronics Reliability, 93, 89–97

    Article  Google Scholar 

  18. Li, J., Xiao, L. Y., Li, H. C., & Qi, C. H. (2018). A low-overhead radiation hardened design flip-flop for soft error detection. In Proceedings of 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). Qingdao, China

  19. Chaudhry, I., K., &, & Anand, B. (2019). High performance energy efficient radiation hardened latch for low voltage applications. Integration, 66, 119–127

    Google Scholar 

  20. Anajemba, J. H., Ansere, J. A., Sam, F., Iwendi, C., & Srivastava, G. (2021). Optimal soft error mitigation in wireless communication using approximate logic circuits. Sustainable Computing: Informatics and Systems, 30, 100521

    Google Scholar 

  21. Wey, I. C., Chen, C. H., Fang, S. Z., & Chou, H. J. (2019). Soft-event-upset and soft-event-transient tolerant cmos circuit design for low-voltage low-power wireless IoT applications. In Proceedings of Eleventh International Conference on Ubiquitous and Future Networks (ICUFN) (pp. 179-181). Zagreb Croatia

Download references

Funding

The authors declare that they have no funding source to be acknowledged.

Author information

Authors and Affiliations

  1. Department of ECE, St. Xavier’s Catholic College of Engineering, Nagercoil, Tamil Nadu, India

    T. Dhanushya & T. Latha

Authors
  1. T. Dhanushya
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. T. Latha
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors read and approved the final manuscript.

Corresponding author

Correspondence to T. Dhanushya.

Ethics declarations

Conflict of Interest

On behalf of all authors, the corresponding author states that there is no conflict of interest.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dhanushya, T., Latha, T. High Reliability Soft Error Hardened Latch Design for Nanoscale CMOS Technology using PVT Variation. Wireless Pers Commun 128, 1471–1487 (2023). https://doi.org/10.1007/s11277-022-10033-4

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-022-10033-4

Keywords

Search

Navigation