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Design of Flexible Floating Point Processing Element (FFPPE) Architecture Based on Golay Code Strategy

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Abstract

In the communication systems, GOLAY code is constantly playing an imperative part as a perfect linear error correcting code of the system. This code is utilized in the forward error correcting appliance for communication acquaintances. Accordingly, in this work, a GOLAY code technique is implemented by designing a novel compact IC (integrated chip) by the use of FFPPE (Flexible Floating Point Processing Element) which is the significant entity for multiplication, subtraction, addition, (ALU) method. Binary data architecture is employed on Cyclic-Redundancy Check methodology with the use of encoder and decoder. Further, the VHDL is used to verify the GCEA (GOLAY code encoder architecture) on FPGA (Field Programmable Gate Array) devices in Xilinx ISE 14.2. The security of the system is increased and the circuit’s complexity level is optimized through this designed architecture. It identifies various types of errors during the data transmission. The encoder and decoder is modified by adding the message bits in the GOLAY and extended GOLAY code techniques. Finally, the performance measures are estimated for the proposed scheme in terms of look up tables (LUT) optimization, area, power, speed, circuit complexity, power utilization, slice count, clock frequency. Comprehensive comparative analysis of the proposed and existing system promotes the understanding of the effectiveness of the proposed system. These parameters include the LUT count, synthesized frequency in MHZ, clock, area as well as speed. The results exhibited that the proposed methodology is efficient than the conventional techniques in enhancing the system security.

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Data Availability

https://doi.org/10.1109/mwc.001.1900494, https://doi.org/10.1109/tvt.2020.3007521, https://doi.org/10.15598/aeee.v16i4.2735, https://doi.org/10.1109/jsyst.2020.2981366, https://doi.org/10.1109/tvlsi.2016.2620998, https://doi.org/10.1109/tcomm.2020.3006212, https://doi.org/10.1109/tvlsi.2018.2837220, https://doi.org/10.1016/j.vlsi.2017.11.010, https://doi.org/10.1049/el.2017.1037, https://doi.org/10.1109/lcomm.2018.2850772, https://doi.org/10.1109/jbhi.2020.2988449, https://doi.org/10.1049/joe.2014.0055, https://doi.org/10.1109/tit.2020.2978383, https://doi.org/10.1007/978-981-10-7191-1_13, https://doi.org/10.1109/tvlsi.2015.2465846, https://doi.org/10.1109/siitme.2018.8599233, https://doi.org/10.5120/ijca2016912242, https://doi.org/10.1109/eiconcit.2018.8878513, https://doi.org/10.1109/54.922807, https://doi.org/10.1109/tc.2003.1234528, https://doi.org/10.1109/tvlsi.2014.2346712.

Code Availability

Not Applicable.

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Funding

This research work was not funded by any organization/institute/agency.

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Authors and Affiliations

  1. Research Scholar, PET Research Center,PES College of Engineering, University of Mysore (UOM), Mandaya, Karnataka, India

    Rupa Kumar Dhanavath

  2. Assistant Professor, Department of Electronics and Communication Engineering, Marri Laxman Reddy Institute of Technology and Management, Hyderabad, Telangana, India

    Rupa Kumar Dhanavath

  3. Department of Electrical and Electronics Engineering, PES College of Engineering, Mandaya, Karnataka, India

    Gopiya Naik Sevyanaik

Authors
  1. Rupa Kumar Dhanavath
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  2. Gopiya Naik Sevyanaik
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Contributions

I am RKD hereby state that the manuscript title entitled “design of flexible floating point processing element (FFPPE) architecture based on GOLAY code strategy” submitted to wireless personal communications, i and my co-author NGN confirm that this work is original and has not been published elsewhere, nor is it currently under consideration for publication elsewhere. and i am assistant professor in Marri Laxman Reddy institute of technology & management, Hyderabad, India.

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Correspondence to Rupa Kumar Dhanavath.

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Dhanavath, R.K., Sevyanaik, G.N. Design of Flexible Floating Point Processing Element (FFPPE) Architecture Based on Golay Code Strategy. Wireless Pers Commun 125, 1783–1800 (2022). https://doi.org/10.1007/s11277-022-09634-w

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  • DOI: https://doi.org/10.1007/s11277-022-09634-w

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