Abstract
Error correcting codes (ECCs) are employed in most of the modern communication systems and semiconductor memories to detect and correct errors introduced by noise and radiation effects, respectively. In these systems, multiple errors are more common nowadays due to the rapid advancement in semiconductor technology. Various types of multi-bit ECCs like Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) codes are capable of handling these multiple errors at the cost of complex decoding method. Alternatively, multi-bit adjacent error correcting codes such as single error correction, double error detection, and double adjacent error correction (SEC-DED-DAEC) and single error correction, double error detection, double adjacent error correction, and triple adjacent error correction (SEC-DED-DAEC-TAEC) codes have comparatively simpler decoder structure for handling multi-bit adjacent errors. But the main drawbacks of these codes are the growing codec design constrains as correction capability increases. In this paper, a new SEC-DED-DAEC-TAEC code has been proposed for the word lengths of 16, 32, and 64 bits. The proposed codecs for three different message lengths have been simulated and synthesized in FPGA platform. The proposed codecs have lower delay compared to the existing-related works. Also miscorrection rate of the proposed codes is lower compared to the related works.
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Maity, R.K., Samanta, J., Bhaumik, J. (2022). FPGA-Based Low Delay Adjacent Triple-Bit Error Correcting Codec. In: Dahal, K., Giri, D., Neogy, S., Dutta, S., Kumar, S. (eds) Internet of Things and Its Applications. Lecture Notes in Electrical Engineering, vol 825. Springer, Singapore. https://doi.org/10.1007/978-981-16-7637-6_37
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DOI: https://doi.org/10.1007/978-981-16-7637-6_37
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