Variability Analysis of SBOX With CMOS 45 nm Technology

Abstract

The consistent scaling of metal-oxide-semiconductor field-effect transistor devices lead to parameter variations which become a significant design challenge for the researchers and designers. This variation deviates the design parameter from specific values and degrades the performance. Process, voltage, and temperature (PVT) variations are uncontrollable natural occurring phenomena during fabrication steps that result in slow and fast MOS transistors. In this paper effect of variability on the performance of the nonlinear cryptographic block substitution box (SBOX) is explored at CMOS 45 nm technology at 1 V supply voltage. Performance parameter optimizes by including underlying cells with different CMOS logic structures like pass transistor logic (PTL) and transmission gate (TG). Power consumption pattern increases with FF corner and decreases towards the SS corner while delay varies differently for SF and FS corner. SBOX underlying cell XOR & AND gate implemented with PTL logic reduces the transistor count and lowers power consumption but at the same time PTL logic enhances delay. For the SBOX with TG logic decreases delay by maintaining power and area under specific limit. Delay and power vary more rapidly for PTL, and TG logic compares to static CMOS logic. The simulation result justifies that voltage and temperature variation is more pronounced at SF and FS corners compared to others. Maximum variation occurs for the delay, at SF corner with − 10% supply variation 307.52% and power at FS corner with + 10% supply variation 99.81%. The process variability of SBOX is majorly oriented towards the cryptographic applications and to access the SBOX vulnerabilities and countermeasures challenges.