The International Conference on Application-specific Systems, Architectures and Processors (ASAP) has a long tradition in various hardware-related research topics, including computer arithmetic, application-specific instruction-set processors and accelerators, heterogeneous computing ranging from embedded systems to computing infrastructures, and reconfigurable computing. The 2020 edition of ASAP  was hosted by the Department of Computer Science at The University of Manchester, UK and took place as a virtual conference during July 6–7, 2020.
This special issue of Springer’s Journal of Signal Processing Systems covers various facets of the topics mentioned afore. The special issue is based on extended contributions of selected top-level papers presented at ASAP 2020 . From 118 submitted papers, 21 long papers had been presented at ASAP 2020, and after a careful peer-review process, four extended manuscripts were accepted for inclusion in this special issue. It is our pleasure to introduce these articles in the following briefly.
The initial two articles of this special issue deal with computer arithmetic.
The first article, “A Reconfigurable Posit Tensor Unit with Variable-Precision Arithmetic and Automatic Data Streaming” by Neves, Tomás, and Roma , deals with the acceleration of deep neural networks (DNNs). The authors propose a reconfigurable tensor unit that deploys an array of variable-precision vector multiply-accumulate units. The new vector unit is compared against existing SIMD units concerning energy efficiency. For a 45nm ASIC implementation, the proposed unit provides an increased performance and energy efficiency over the existing state-of-the-art tensor and SIMD units that are present in off-the-shelf chips.
The second article, “Efficient Floating-Point Implementation of the Probit Function on FPGAs” by Joldes and Pasca , revisits floating-point implementations of probit, which is the quantile function associated with the standard normal distribution. More specifically, the authors utilize embedded floating-point DSP blocks of recent FPGA families. The proposed implementations outperform existing single-precision floating-point FPGA realizations in terms of area, latency, and accuracy.
The following two articles deal with heterogeneous accelerator systems.
The article with the title “How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System,” by Asiatici, Maiorano, and Ienne , presents a parallel hybrid superscalar string sample sorter on Intel HARPv2, a heterogeneous CPU-FPGA system. The authors discuss the performance and energy advantages of FPGA-based systems in different data center settings. A dedicated aspect of this work is a sorting architecture for variable-length strings.
Vandebon, Coutinho, and Luk  provide the last article, “Scheduling Hardware-Accelerated Cloud Functions.” The authors present a Function-as-a-Service (FaaS) approach for deploying managed cloud functions onto heterogeneous cloud infrastructures. The FaaS approach is validated for several applications stemming from machine learning, bioinformatics, and physics.
At the end of this editorial, we want to thank everybody who contributed to this special issue. We are very grateful to the editor-in-chief, Sun-Yuan Kung, and the co-editors-in-chief, Shuvra S. Bhattacharyya and Jarmo Takala, of Springer’s Journal of Signal Processing Systems. We also acknowledge the administrative staff for their valuable support throughout the preparation and publication of this special issue. Furthermore, we thank all authors for their contributions to this special issue and their excellent efforts. Finally, we also thank all the reviewers for their careful work and valuable suggestions that helped improve the quality of the articles.